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74LVC00A

nexperia
Part Number 74LVC00A
Manufacturer nexperia
Description Quad 2-input NAND gate
Published Jul 23, 2019
Detailed Description 74LVC00A Quad 2-input NAND gate Rev. 9 — 17 September 2021 Product data sheet 1. General description The 74LVC00A is a...
Datasheet PDF File 74LVC00A PDF File

74LVC00A
74LVC00A

Overview
74LVC00A Quad 2-input NAND gate Rev.
9 — 17 September 2021 Product data sheet 1.
General description The 74LVC00A is a quad 2-input NAND gate.
Inputs can be driven from either 3.
3 V or 5 V devices.
This feature allows the use of these devices as translators in mixed 3.
3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
2.
Features and benefits • Overvoltage tolerant inputs to 5.
5 V • Wide supply voltage range from 1.
2 V to 3.
6 V • CMOS low-power consumption • Direct interface with TTL levels • Complies with JEDEC standard: • JESD8-7A (1.
65 V to 1.
95 V) • JESD8-5A (2.
3 V to 2.
7 V) • JESD8-C/JESD36 (2.
7 V to 3.
6 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74LVC00AD -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.
9 mm 74LVC00APW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
4 mm 74LVC00ABQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5 × 3 × 0.
85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4.
Functional diagram 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 2Y 6 3Y 8 4Y 11 mna212 Fig.
1.
Logic symbol 1 2 & 3 4 5 & 6 9 10 & 8 12 13 & 11 mna246 Fig.
2.
IEC logic symbol 5.
Pinning information 74LVC00A Quad 2-input NAND gate A Y B mna211 Fig.
3.
Logic diagram (one gate) 5.
1.
Pinning 74LVC00A 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y 001aac938 Fig.
4.
Pin configuration for SOT108-1 (SO14) and SOT402-1 (TSSOP14) 74LVC00A 1 1A 14 VCC terminal 1 index area 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND (1) ...


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