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IDT72201

Part Number	IDT72201
Manufacturer	Renesas
Description	CMOS SyncFIFO
Published	Jan 19, 2020
Detailed Description	CMOS SyncFIFO™ IDT72421, IDT72201 64 x 9, 256 x 9, 512 x 9, IDT72211, IDT72221 1,024 x 9, 2,048 x 9, IDT72231, IDT7...
Datasheet	IDT72201 PDF File

Overview

CMOS SyncFIFO™ IDT72421, IDT72201 64 x 9, 256 x 9, 512 x 9, IDT72211, IDT72221 1,024 x 9, 2,048 x 9, IDT72231, IDT72241 4,096 x 9 and 8,192 x 9 IDT72251 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: • 64 x 9-bit organization (IDT72421) • 256 x 9-bit organization (IDT72201) • 512 x 9-bit organization (IDT72211) • 1,024 x 9-bit organization (IDT72221) • 2,048 x 9-bit organization (IDT72231) • 4,096 x 9-bit organization (IDT72241) • 8,192 x 9-bit organization (IDT72251) • 10 ns read/write cycle time • Read and Write Clocks can be independent • Dual-Ported zero fall-through time architecture • Empty and Full Flags signal FIFO status • Programmable Almost-Empty and Almost-Full flags can be set to any depth • Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively • Output enable puts output data bus in high-impedance state • Advanced submicron CMOS technology • Available in the 32-pin plastic leaded chip carrier (PLCC) and 32-pin Thin Quad Flat Pack (TQFP) • For through-hole product please see the IDT72420/72200/72210/ 72220/72230/72240 data sheet • Industrial temperature range (–40°C to +85°C) is available • Green parts available, see ordering information DESCRIPTION: The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™ are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls.
These devices have a 64, 256, 512, 1,024, 2,048, 4,096, and 8,192 x 9-bit memory array, respectively.
These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication.
These FIFOs have 9-bit input and output ports.
The input port is controlled by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).
Data is written into the Synchronous FIFO on every rising clock edge when the write enable pins are asserted.
The output port is controlled by another clock pin (RCLK) and tw...

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