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IDT72211

Integrated Device Technology
Part Number IDT72211
Manufacturer Integrated Device Technology
Description FIFO memories
Published Apr 4, 2005
Detailed Description IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 CMOS Sy...
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IDT72211
IDT72211

Overview
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 CMOS SyncFIFO™ 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES Integrated Device Technology, Inc.
IDT72421 IDT72201 IDT72211 IDT72221 IDT72231 IDT72241 FEATURES: • • • • • • • • • • • • • • • • • • 64 x 9-bit organization (IDT72421) 256 x 9-bit organization (IDT72201) 512 x 9-bit organization (IDT72211) 1024 x 9-bit organization (IDT72221) 2048 x 9-bit organization (IDT72231) 4096 x 9-bit organization (IDT72241) 12 ns read/write cycle time (IDT72421/72201/72211) 15 ns read/write cycle time (IDT72221/72231/72241) Read and write clocks can be independent Dual-Ported zero fall-through time architecture Empty and Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags can be set to any depth Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively Output enable puts output data bus in high-impedance state Advanced submicron CMOS technology Available in 32-pin plastic leaded chip carrier (PLCC), ceramic leadless chip carrier (LCC), and 32-pin Thin Quad Flat Pack (TQFP) For Through-Hole product please see the IDT72420/ 72200/72210/72220/72230/72240 data sheet Military product compliant to MIL-STD-883, Class B DESCRIPTION: The IDT72421/72201/72211/72221/72231/72241 SyncFIFO™ are very high-speed, low-power First-In, First- Out (FIFO) memories with clocked read and write controls.
The IDT72421/72201/72211/72221/72231/72241 have a 64, 256, 512, 1024, 2048, and 4096 x 9-bit memory array, respectively.
These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication.
These FIFOs have 9-bit input and output ports.
The input port is controlled by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).
Data is written into the Synchronous FIFO on every rising clock ed...


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