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AM6526

Texas Instruments
Part Number AM6526
Manufacturer Texas Instruments
Description Processors
Published Apr 15, 2020
Detailed Description AM6548, AM6528, AM6546, AM6526 SPRSP52C – DECEMBER 2019 – REVISED SEPTEMBER 2023 AM654x, AM652x Sitara™ Processors Silic...
Datasheet PDF File AM6526 PDF File

AM6526
AM6526

Overview
AM6548, AM6528, AM6546, AM6526 SPRSP52C – DECEMBER 2019 – REVISED SEPTEMBER 2023 AM654x, AM652x Sitara™ Processors Silicon Revision 2.
1 1 Features Processor cores: • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.
1 GHz – Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED – Each A53 core has 32KB L1 ICache and 32K L1 DCache • Dual-core Arm® Cortex®-R5F at up to 400 MHz – Supports lockstep mode – 16KB ICache, 16KB DCache, and 64KB RAM per R5F core Industrial subsystem: • Three gigabit Industrial Communication Subsystems (PRU_ICSSG) – Up to two 10/100/1000 Ethernet ports per PRU_ICSSG – Supports two SGMII ports(2) – Compatibility with 10/100Mb PRU-ICSS – 24× PWMs per PRU_ICSSG • Cycle-by-cycle control • Enhanced trip control – 18× Sigma-delta filters per PRU_ICSSG • Short circuit logic • Over-current logic – 6× Multi-protocol position encoder interfaces per PRU_ICSSG Memory subsystem: • Up to 2MB of on-chip L3 RAM with SECDED • Multi-core Shared Memory Controller (MSMC) – Up to 2MB (2 banks × 1MB) SRAM with SECDED • Shared coherent Level 2 or Level 3 memory-mapped SRAM • Shared coherent Level 3 Cache – 256-bit processor port bus and 40-bit physical address bus – Coherent unified bi-directional interfaces to connect to processors or device masters – L2, L3 Cache pre-warming and post flushing – Bandwidth management with starvation bound – One infrastructure master interface – Single external memory master interface – Supports distributed virtual system – Supports internal DMA engine – Data Routing Unit (DRU) – ECC error protection • DDR Subsystem (DDRSS) – Supports DDR4 memory types up to DDR-1600 – 32-bit data bus and 7-bit SECDED bus – 8 GB of total addressable space • General-Purpose Memory Controller (GPMC) Functional Safety: • Functional Safety-Compliant [Industrial] – Developed for functional safety applications – Documentation available to aid IEC 61508 functional safety system design – ...


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