DatasheetsPDF.com

9DBL0843

Part Number	9DBL0843
Manufacturer	Renesas
Description	LP-HCSL Zero-Delay Buffer
Published	Jun 4, 2020
Detailed Description	8-output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator 9DBL08x3 Datasheet General Description The 9DBL08x3 devices...
Datasheet	9DBL0843 PDF File

Overview

8-output 3.
3V LP-HCSL Zero-Delay Buffer with LOS Indicator 9DBL08x3 Datasheet General Description The 9DBL08x3 devices are 3.
3V members of IDT's Full-Featured PCIe clock family.
They support PCIe Gen1-4 Common Clock (CC) architectures and also support NVLINK applications.
The 9DBL08x3 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high reliability systems.
Recommended Application PCIe Gen1-4 and NVLINK clock distribution for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Output Features ▪ Loss Of Signal (LOS) open drain output ▪ 8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs ▪ 9DBL0843 default Zout = 100Ω ▪ 9DBL0853 default Zout = 85Ω ▪ Easy AC-coupling to other logic families, see IDT application note AN-891.
Key Specifications ▪ PCIe Gen1-4 CC compliant in ZDB or fanout buffer mode ▪ Supports NVLINK at 156.
25M in ZDB or fanout buffer mode ▪ DIF cycle-to-cycle jitter <50ps ▪ DIF output-to-output skew < 50ps ▪ Bypass mode additive phase jitter is 0 ps typical rms for PCIe ▪ Bypass mode additive phase jitter 160fs rms typ.
@ 156.
25M (1.
5M to 10M) Block Diagram vOE(7:0)# 7 Features/Benefits ▪ LOS indicator signals loss of input clock; adds fault tolerance, eases system diagnostics ▪ Direct connection to 100Ω (xx43) or 85Ω (xx53) transmission lines; saves 32 resistors compared to standard PCIe devices ▪ 205mW typical power consumption (PLL mode@3.
3V); eliminates thermal concerns ▪ VDDIO allows >33% power savings at optional 1.
05V; maximum power savings ▪ OE# pin for each DIF output; support DIF power management ▪ HCSL-compatible differential input; can be driven by common clock sources ▪ Spread Spectrum tolerant; allows reduction of EMI ▪ Outputs blocked until PLL is locked; clean system start-up ▪ Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application ▪ Device contains default configuration; SMBus interface not required for device operation ▪ 3 selectable SMBus addresses; multiple ...

Similar Datasheet

9DBL08 8-output 3.3V PCIe Zero-Delay Buffer - IDT
9DBL0841 Zero-Delay/Fanout Buffer - Renesas
9DBL0841 8-output 3.3V PCIe Zero-Delay Buffer - IDT
9DBL0841C 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers - Renesas
9DBL0843 LP-HCSL Zero-Delay Buffer - Renesas
9DBL0843 8-output 3.3V LP-HCSL Zero-Delay Buffer - IDT
9DBL0851 8-output 3.3V PCIe Zero-Delay Buffer - IDT
9DBL0851C 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers - Renesas
9DBL0853 LP-HCSL Zero-Delay Buffer - Renesas
9DBL0853 8-output 3.3V LP-HCSL Zero-Delay Buffer - IDT

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)