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82P33741

Part Number	82P33741
Manufacturer	Renesas
Description	Port Synchronizer
Published	Aug 13, 2020
Detailed Description	Port Synchronizer for IEEE 1588 and 10G/ 40G/ 100G Synchronous Ethernet 82P33741 Datasheet HIGHLIGHTS • DPLL1 and DPLL...
Datasheet	82P33741 PDF File

Overview

Port Synchronizer for IEEE 1588 and 10G/ 40G/ 100G Synchronous Ethernet 82P33741 Datasheet HIGHLIGHTS • DPLL1 and DPLL2 can be used on line cards to manage the generation of synchronous port clocks and IEEE 1588 synchronization signals based on multiple system backplane references • DPLL3 can be used on line cards to select incoming line clocks for use on system backplanes; it can also be used for general purpose timing applications • APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to 20 MHz) for: 1000BASE-T and 1000BASE-X ports and to generate IEEE 1588 time stamp clocks and 1 pulse per second (PPS) signals • APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and generates clocks with jitter <0.
3 ps RMS (10 kHz to 20 MHz) for: 10GBASE-R, 10GBASE-W, 40GBASE-R and 100GBASE-R • Fractional-N input dividers support a wide range of reference frequencies • DPLLs, APLL1 and APLL2 can be configured from an external EEPROM after reset FEATURES • Differential reference inputs (IN1 to IN6) accept clock frequencies between 2 kHz and 650 MHz • Single ended inputs (IN7 to IN12) accept reference clock frequencies between 2 kHz and 162.
5 MHz • Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input • Reference monitors qualify/disqualify references depending on activity, frequency and LOS pins • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings • Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G/ 40G/100G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM and GNSS frequencies • Any reference inputs (IN1 to IN12) can be designated as external sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a selectable reference clock input • FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses that...

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