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74HC191D

Part Number	74HC191D
Manufacturer	nexperia
Description	Presettable synchronous 4-bit binary up/down counter
Published	Dec 26, 2020
Detailed Description	74HC191 Presettable synchronous 4-bit binary up/down counter Rev. 6 — 8 September 2021 Product data sheet 1. General...
Datasheet	74HC191D PDF File

Overview

74HC191 Presettable synchronous 4-bit binary up/down counter Rev.
6 — 8 September 2021 Product data sheet 1.
General description The 74HC191 is an asynchronously presettable 4-bit binary up/down counter.
It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.
Asynchronous parallel load capability permits the counter to be preset to any desired value.
Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW.
This operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable (CE) input.
When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input.
The up/down (U/D) input signal determines the direction of counting as indicated in the function table.
The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH.
Also, the U/D input should be changed only when either CE or CP is HIGH.
Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC).
The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches '15' in the count-up-mode.
The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed.
Do not use the TC output as a clock signal because it is subject to decoding spikes.
The TC signal is used internally to enable the RC output.
When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP).
This feature simplifies the design of multistage counters as shown in Fig.
5 and Fig.
6.
In Fig.
5, each RC output is used as the clock input to the next higher stage.
It is only necessary to inhibit the first stage to prevent counting in all sta...

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