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MT9125

MITEL

Dual ADPCM Transcoder

CMOS MT9125 ® Dual ADPCM Transcoder Preliminary Information Features • Dual channel full duplex transcoder • 32 kbit/s ...


MT9125

MITEL


Octopart Stock #: O-1496768

Findchips Stock #: 1496768-F

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Description
CMOS MT9125 ® Dual ADPCM Transcoder Preliminary Information Features • Dual channel full duplex transcoder • 32 kbit/s and 24 kbit/s ADPCM coding, • compatible to G.721 & and G.723 (1988) and ANSI T1.303-1989 • Low power operation, total 25mW typical • Asynchronous 4.096 MHz master clock operation • Transparent ADPCM bypass capability • Serial int
More View erface for both PCM and ADPCM data streams • ST-BUS interface supported • Pin selected µ-law or A-law operation • Pin selected CCITT or sign-magnitude PCM coding • Single 5 volt power supply • Optional reset value (CCITT Table 3/G.721) capability Applications • Pair gain • Voice mail systems • Wireless set base stations ISSUE 3 Ordering Information August 1993 MT9125AE MT9125AP 24 Pin Plastic DIP 28 Pin PLCC -40 to +85°C Description The Dual-channel ADPCM transcoder is a low power, CMOS device capable of two encoder functions and two decoder functions. Two 64 kbit/s PCM channels are compressed into two 32 kbit/s ADPCM channels, and two 32 kbit/s ADPCM channels are expanded into two 64 kbit/s PCM channels. The 32 kbit/s ADPCM transcoding algorithm utilized conforms to CCITT Recommendation G.721 and ANSI T1.303-1989. The device also supports a 24 kbit/s (three bit word) algorithm (CCITT/G.723). Switching, on-the-fly, between 32 kbit/s and 24 kbit/s, is possible by toggling the appropriate Mode Select (MS1-MS4) control pins. C2o BCLK F0i MCLK ENS ADPCMi ADPCMo ENA Timing ST-BUS Converter ADPCM I/O Transcoder 1 Transcoder 2 PCM I/O Control Decode EN1 EN2 DSTo DSTi ENB1 ENB2 VDD VSS PWRDN IC MS1 MS2 A/µ FORMAT MS3 MS4 Figure 1 - Functional Block Diagram 8-17 MT9125 24 PIN PDIP Preliminary Information MCLK 1 F0i 2 C2o 3 DSTo 4 DSTi 5 BCLK 6 VSS 7 ENB2 8 ENB1 9 MS1 10 MS2 11 MS3 12 24 ENS 23 EN2 22 EN1 21 ADPCMo 20 ADPCMi 19 ENA 18 VDD 17 IC 16 PWRDN 15 FORMAT 14 A/µ 13 MS4 4 MCLK 3 F0i 2 C2o 1 NC 28 ENS 27 EN2 26 EN1 28 PIN PLCC DSTo 5 • 25 ADPCMo DSTi 6 24 ADPCMi BCLK 7 23 ENA VSS 8 22 VDD NC 9 21 NC ENB2 10 20 IC ENB1 11 19 PWRDN MS1 12 MS2 13 MS3 14 NC 15 MS4 16 A/µ 17 FORMAT 18 Pin Description Figure 2 - Pin Connections Pin # DIP PLCC 12 Name Description MCLK Master Clock input. This 4.096 MHz clock is used as an internal master clock and must be provided during both ST-BUS and SSI modes of operation. This is a TTL level input. In ST-BUS mode the MCLK input (also known as C4i in ST-BUS terms) is derived from the synchronous 4.096 MHz clock available from the layer 1 transceiver device. The C4i clock, input to MCLK, is used in this mode as both the internal master clock and for deriving the C2o output clock and EN1/EN2 output enable strobes. 23 34 45 56 F0i C2o DSTo DSTi In SSI mode a 4.096 MHz master clock must be derived from an external source. This master clock may be asynchronous relative to the 8 kHz f






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