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MT9123

MITEL

Dual Voice Echo Canceller

CMOS MT9123 ® Dual Voice Echo Canceller Preliminary Information Features • Dual channel 64ms or single channel 128ms ec...


MT9123

MITEL


Octopart Stock #: O-1496771

Findchips Stock #: 1496771-F

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Description
CMOS MT9123 ® Dual Voice Echo Canceller Preliminary Information Features • Dual channel 64ms or single channel 128ms echo cancellation • Conforms to ITU-T G.165 requirements • Narrow-band signal detection • Programmable double-talk detection threshold • Non-linear processor with adaptive suppression threshold and comfort noise insertion • Offset n
More View ulling of all PCM channels • Controllerless mode or Controller mode with serial interface • ST-BUS or variable-rate SSI PCM interfaces • Selectable µ/A-Law ITU-T G.711; µ/A-Law Sign Mag; linear 2’s complement • Per channel selectable 12 dB attenuator • Transparent data transfer and mute option • 19.2 MHz master clock operation Applications • Wireless Telephony • Trunk echo cancellers ISSUE 1 October 1996 Ordering Information MT9123AP 28 Pin PLCC MT9123AE 28 Pin PDIP -40 °C to + 85 °C Description The MT9123 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.165 requirements. The MT9123 architecture contains two echo cancellers which can be configured to provide dual channel 64 millisecond echo cancellation or single channel 128 millisecond echo cancellation. The MT9123 operates in two major modes: Controller or Controllerless. Controller mode allows access to an array of features for customizing the MT9123 operation. Controllerless mode is for applications where default register settings are sufficient. Sin Rout ENA2 ENB2 NLP LAW FORMAT IC3 IC4 Linear/ µ/A-Law Programmable Bypass Offset Null + - Adaptive Filter Control Non-Linear Processor Linear/ µ/A-Law Microprocessor Interface Double-Talk Detector Narrow-Band Detector Linear/ µ/A-Law 12dB Attenuator Offset Null Linear/ µ/A-Law Echo Canceller A Echo Canceller B Sout Rin ENA1 ENB1 CONFIG1 CONFIG2 S1/DATA1 S2/DATA2 S3/CS S4/SCLK IC1 IC2 VDD VSS PWRDN F0od F0i BCLK/C4i MCLK Figure 1 - Functional Block Diagram 8-45 MT9123 Preliminary Information 4 ENB2 3 ENA2 2 ENB1 1 ENA1 28 CONFIG2 27 CONFIG1 26 BCLK/C4i ENA1 ENB1 ENA2 ENB2 Rin Sin VSS MCLK IC1 NLP IC2 LAW FORMAT PWRDN 1 28 2 27 3 26 4 25 5 24 6 PDIP 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 CONFIG2 CONFIG1 BCLK/C4i F0i Rout Sout VDD F0od S1/DATA1 S2/DATA2 S3/CS S4/SCLK IC4 IC3 Rin 5 Sin 6 VSS 7 MCLK 8 IC1 9 NLP 10 IC2 11 • PLCC 25 F0i 24 Rout 23 Sout 22 VDD 21 F0od 20 S1/DATA1 19 S2/DATA2 LAW 12 FORMAT 13 PWRDN 14 IC3 15 IC4 16 S4/SCLK 17 S3/CS 18 Figure 2 - Pin Connections Pin Description Pin # 1 Name ENA1 Description SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS is selected. For SSI, this strobe must be present for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer






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