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TMS320DM8147

Texas Instruments
Part Number TMS320DM8147
Manufacturer Texas Instruments
Description Video Processors
Published Dec 17, 2022
Detailed Description TMS320DM8148, TMS320DM8147 www.ti.com SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 TMS320DM814x DaVinci™ Video Proces...
Datasheet PDF File TMS320DM8147 PDF File

TMS320DM8147
TMS320DM8147

Overview
TMS320DM8148, TMS320DM8147 www.
ti.
com SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 TMS320DM814x DaVinci™ Video Processors Check for Samples: TMS320DM8148, TMS320DM8147 1 High-Performance System-on-Chip (SoC) 1.
1 Features 12 • High-Performance DaVinci Video Processors – Up to 1-GHz ARM® Cortex®-A8 RISC Core – Up to 750-MHz C674x™ VLIW DSP – Up to 6000 MIPS and 4500 MFLOPS – Fully Software-Compatible with C67x+™, C64x+™ • ARM Cortex-A8 Core – ARMv7 Architecture • In-Order, Dual-Issue, Superscalar Processor Core • Neon™ Multimedia Architecture • Supports Integer and Floating Point • Jazelle® RCT Execution Environment • ARM Cortex-A8 Memory Architecture – 32KB of Instruction and Data Caches – 512KB of L2 Cache – 64KB of RAM, 48KB of Boot ROM • TMS320C674x Floating-Point VLIW DSP – 64 General-Purpose Registers (32-Bit) – 32KB of L1D RAM/Cache – 256KB of L2 Unified Mapped RAM/Caches With ECC • System Memory Management Unit (MMU) – Maps C674x DSP and EDMA TC Memory Accesses to System Addresses • 128KB of On-Chip Memory Controller (OCMC) RAM • Imaging Subsystem (ISS) – Camera Sensor Connection • Parallel Connection for Raw (up to 16-Bit) and BT.
656 or BT.
1120 (8- and 16-Bit) – Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor – Resizer • Resizing Image and Video From 1/16x to 8x • Generating Two Different Resizing Outputs Concurrently – Six ALU (32-/40-Bit) Functional Units • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle – Two Multiply Functional Units • Mixed-Precision IEEE Floating-Point Multiply Supported up to: – 2 SP x SP → SP Per Clock – 2 SP x SP → DP Every Two Clocks – 2 SP x DP → DP Every Three Clocks – 2 DP x DP → DP Every Four Clocks • Fixed-Point Multiply Supports Two 32 x 32 M...


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