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TMS320DM8165

Texas Instruments
Part Number TMS320DM8165
Manufacturer Texas Instruments
Description Digital Media Processors
Published Dec 17, 2022
Detailed Description Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320DM8168, TMS320DM8167 TMS...
Datasheet PDF File TMS320DM8165 PDF File

TMS320DM8165
TMS320DM8165

Overview
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320DM8168, TMS320DM8167 TMS320DM8165 SPRS614F – MARCH 2011 – REVISED MARCH 2015 TMS320DM816x DaVinci™ Digital Media Processors 1 Device Overview 1.
1 Features 1 • High-Performance DaVinci Digital Media Processors – ARM® Cortex™-A8 RISC Processor • Up to 1.
20 GHz – C674x™ VLIW DSP • Up to 1 GHz • Up to 8000 MIPS and 6000 MFLOPS • Fully Software-Compatible with C67x+ and C64x+™ • ARM Cortex-A8 Core – ARMv7 Architecture • In-Order, Dual-Issue, Superscalar Processor Core • NEON™ Multimedia Architecture – Supports Integer and Floating Point (VFPv3IEEE754 Compliant) • Jazelle® RCT Execution Environment • ARM Cortex-A8 Memory Architecture – 32-KB Instruction and Data Caches – 256-KB L2 Cache – 64-KB RAM, 48-KB of Boot ROM • TMS320C674x Floating-Point VLIW DSP – 64 General-Purpose Registers (32-Bit) – Six ALU (32-Bit and 40-Bit) Functional Units • Supports 32-Bit Integer, SP (IEEE Single Precision, 32-Bit) and DP (IEEE Double Precision, 64-Bit) Floating Point • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle – Two Multiply Functional Units • Mixed-Precision IEEE Floating-Point Multiply Supported up to: – 2 SP x SP → SP Per Clock – 2 SP x SP → DP Every Two Clocks – 2 SP x DP → DP Every Three Clocks – 2 DP x DP → DP Every Four Clocks • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8Bit Multiplies per Clock Cycle • C674x Two-Level Memory Architecture – 32-KB L1P and L1D RAM and Cache – 256-KB L2 Unified Mapped RAM and Caches 1 • System Memory Management Unit (System MMU) – Maps C674x DSP and EMDA TCB Memory Accesses to System Addresses • 512KB of On-Chip Memory Controller (OCMC) RAM • Media Controller – Manages HDVPSS and HDVICP2 Modules • Up to Three Programmable High-Definitio...


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