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54HC112

Part Number	54HC112
Manufacturer	Texas Instruments
Description	Dual J-K Negative-Edge-Triggered Flip-Flops
Published	Apr 27, 2023
Detailed Description	SN54HC112, SN74HC112 SCLS099H – DECEMBER 1982 – REVISED JUNE 2022 SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops ...
Datasheet	54HC112 PDF File

Overview

SN54HC112, SN74HC112 SCLS099H – DECEMBER 1982 – REVISED JUNE 2022 SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 1 Features • Wide operating voltage range of 2 V to 6 V • Outputs can drive up to 10 LSTTL loads • Low power consumption, 40-μA max ICC • Typical tpd = 13 ns • ±4-mA output drive at 5 V • Low input current of 1 μA max 2 Description The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse.
Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse.
Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs.
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