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SN54ABT16823

Texas Instruments
Part Number SN54ABT16823
Manufacturer Texas Instruments
Description 18-BIT BUS-INTERFACE FLIP-FLOPS
Published May 20, 2023
Detailed Description D Members of the Texas Instruments Widebus ™ Family D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Pow...
Datasheet PDF File SN54ABT16823 PDF File

SN54ABT16823
SN54ABT16823

Overview
D Members of the Texas Instruments Widebus ™ Family D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D High-Impedance State During Power Up and Power Down D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D Flow-Through Architecture Optimizes PCB Layout D High-Drive Outputs (–32-mA IOH, 64-mA IOL ) D Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings description These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads.
They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
SN54ABT16823, SN74ABT16823 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS217C – JUNE 1992 – REVISED JANUARY 1997 SN54ABT16823 .
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WD PACKAGE SN74ABT16823 .
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DGG OR DL PACKAGE (TOP VIEW) 1CLR 1 1OE 2 1Q1 3 GND 4 1Q2 5 1Q3 6 VCC 7 1Q4 8 1Q5 9 1Q6 10 GND 11 1Q7 12 1Q8 13 1Q9 14 2Q1 15 2Q2 16 2Q3 17 GND 18 2Q4 19 2Q5 20 2Q6 21 VCC 22 2Q7 23 2Q8 24 GND 25 2Q9 26 2OE 27 2CLR 28 56 1CLK 55 1CLKEN 54 1D1 53 GND 52 1D2 51 1D3 50 VCC 49 1D4 48 1D5 47 1D6 46 GND 45 1D7 44 1D8 43 1D9 42 2D1 41 2D2 40 2D3 39 GND 38 2D4 37 2D5 36 2D6 35 VCC 34 2D7 33 2D8 32 GND 31 2D9 30 2CLKEN 29 2CLK The ’ABT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop.
With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock.
Taking CLKEN high disables the clock buffer, latching the outputs.
Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.
A buffer...


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