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HM62W16256B

Part Number	HM62W16256B
Manufacturer	Hitachi Semiconductor
Description	4 M SRAM (256-kword x 16-bit)
Published	Mar 26, 2005
Detailed Description	HM62W16256B Series 4 M SRAM (256-kword × 16-bit) ADE-203-934C (Z) Rev. 2.0 Oct. 14, 1999 Description The Hitachi HM62W...
Datasheet	HM62W16256B PDF File

Overview

HM62W16256B Series 4 M SRAM (256-kword × 16-bit) ADE-203-934C (Z) Rev.
2.
0 Oct.
14, 1999 Description The Hitachi HM62W16256B Series is 4-Mbit static RAM organized 262,144-word × 16-bit.
HM62W16256B Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology.
It offers low power standby power dissipation; therefore, it is suitable for battery backup systems.
It is packaged in standard 44-pin plastic TSOPII.
Features • • • Single 3.
3 V supply: 3.
3 V ± 0.
3 V Fast access time: 55 ns/70 ns (max) Power dissipation:  Active: 9.
9 mW (typ)  Standby: 3.
3 µW (typ) Completely static memory.
 No clock or timing strobe required Equal access and cycle times Common data input and output.
 Three state output Battery backup operation.
 2 chip selection for battery backup • • • • HM62W16256B Series Ordering Information Type No.
HM62W16256BLTT-5 HM62W16256BLTT-7 HM62W16256BLTT-5SL HM62W16256BLTT-7SL Access time 55 ns 70 ns 55 ns 70 ns Package 400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DB) 2 HM62W16256B Series Pin Arrangement 44-pin TSOP A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12 Pin Description Pin name A0 to A17 I/O0 to I/O15 CS1 CS2 WE OE LB UB VCC VSS Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte select Upper byte select Power supply Ground 3 HM62W16256B Series Block Diagram LSB V CC V SS • • • • • A4 A3 A15 A14 A16 A1 A2 A17 A0 A13 Row decoder Memory matrix 2,048 x 2,048 MSB I/O0 Input data control I/O15 • • Column I/O Column decoder • • LSB A7 A6 A5 A8 A9A10A11 A12MSB • • CS2 CS1 LB UB WE OE Control logic 4 HM62W16256B Series Operation Table CS1 H × × ...

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