DatasheetsPDF.com

CXL5512M

Part Number	CXL5512M
Manufacturer	Sony Corporation
Description	CMOS-CCD 1H Delay Line for NTSC
Published	Mar 27, 2005
Detailed Description	CXL5512M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5512M/P are CMOS-CCD delay line ICs designed for processin...
Datasheet	CXL5512M PDF File

Overview

CXL5512M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5512M/P are CMOS-CCD delay line ICs designed for processing video signals.
This ICs provide a 1H delay time for NTSC signals including the external lowpass filter.
Features • Single 5 V power supply • Low power consumption • Built-in peripheral circuit • Built-in tripling PLL circuit • Sync tip clamp mode Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD +6 • Operating temperature Topr –10 to +60 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD CXL5512M 350 CXL5512P 480 Recommended Operating Range (Ta=25 ˚C) VDD 5 V±5 % Recommended Clock Conditions (Ta=25 ˚C) • Input clock amplitude VCLK 400mVp-p (Typ.
) • Clock frequency fCLK 3.
579545 MHz • Input clock waveform Sine wave Block Diagram and Pin Configuration VDD VCO OUT VCO IN CLK CXL5512M 8 pin SOP (Plastic) CXL5512P 8 pin DIP (Plastic) Input Signal Amplitude VSIG 500mVp-p (typ.
), 572 mVp-p (max.
) (at internal clamp condition) Functions • 680-bit CCD register • Clock driver • Auto-bias circuit • Sync tip clamp circuit • Sample and hold circuit • Tripling PLL circuit • Inverted output Structure CMOS-CCD V °C °C mW mW 8 7 6 5 PLL Auto-bias circuit Timing circuit CCD (680bit) Output circuit (S/H 1 bit) Clamp circuit Clock driver Bias circuit A Bias circuit B 1 IN 2 AB 3 OUT 4 VSS Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1— E93Y19-TE CXL5512M/P Pin Description Pin No.
1 2 3 4 5 6 7 8 Symbol IN AB OUT VSS CLK VCO IN VCO OUT VDD I/O I O O – I I O – Description Signal input Auto-bias DC output Signal output GND Clock input (fsc) VCO input VCO output (3fsc) 5 V power suppl...

Similar Datasheet

CXL5512M CMOS-CCD 1H Delay Line for NTSC - Sony Corporation
CXL5512P CMOS-CCD 1H Delay Line for NTSC - Sony Corporation
CXL5513M CMOS-CCD 1H Delay Line for NTSC - Sony Corporation
CXL5513P CMOS-CCD 1H Delay Line for NTSC - Sony Corporation
CXL5514M CMOS-CCD 1H Delay Line for PAL - Sony Corporation
CXL5514P CMOS-CCD 1H Delay Line for PAL - Sony Corporation
CXL5515M CMOS-CCD 1H Delay Line for PAL - Sony Corporation
CXL5515P CMOS-CCD 1H Delay Line for PAL - Sony Corporation

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)