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4069UB

ON Semiconductor
Part Number 4069UB
Manufacturer ON Semiconductor
Description Hex Inverter
Published Mar 30, 2005
Detailed Description MC14069UB Hex Inverter The MC14069UB hex inverter is constructed with MOS P−channel and N−channel enhancement mode devi...
Datasheet PDF File 4069UB PDF File

4069UB
4069UB

Overview
MC14069UB Hex Inverter The MC14069UB hex inverter is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure.
These inverters find primary use where low power dissipation and/or high noise immunity is desired.
Each of the six inverters is a single stage to minimize propagation delays.
Features • Supply Voltage Range = 3.
0 Vdc to 18 Vdc • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Triple Diode Protection on All Inputs • Pin−for−Pin Replacement for CD4069UB • Meets JEDEC UB Specifications • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD Vin, Vout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) −0.
5 to +18.
0 V −0.
5 to VDD + 0.
5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range Tstg Storage Temperature Range −55 to +125 °C −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device.
If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1.
Temperature Derating: “D/DW” Packages: –7.
0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit.
For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.
g.
, ...


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