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4069UB

NXP
Part Number 4069UB
Manufacturer NXP
Description Hex inverter
Published Mar 30, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family ...
Datasheet PDF File 4069UB PDF File

4069UB
4069UB

Overview
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4069UB gates Hex inverter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Hex inverter DESCRIPTION The HEF4069UB is a general purpose hex inverter.
Each of the six inverters is a single stage.
HEF4069UB gates Fig.
2 Pinning diagram.
HEF4069UBP(N): HEF4069UBD(F): HEF4069UBT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.
1 Functional diagram.
FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages Fig.
3 Schematic diagram (one inverter).
January 1995 2 Philips Semiconductors Product specification Hex inverter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW LOW to HIGH Output transition times HIGH to LOW 5 10 15 5 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL SYMBOL TYP.
MAX.
45 20 15 40 20 15 60 30 20 60 30 20 90 ns 40 ns 25 ns 80 ns 40 ns 30 ns 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns HEF4069UB gates TYPICAL EXTRAPOLATION FORMULA 18 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 13 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 600 fi + ∑ (foCL) × VDD2 4 000 fi + ∑ (foCL) × 22 000 fi + ∑ (foCL) × VDD2 VDD2 where fi = input freq.
(MHz) fo = output freq.
(MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 Philips Semiconductors Product specificat...


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