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74AHC123A

NXP
Part Number 74AHC123A
Manufacturer NXP
Description Dual retriggerable monostable multivibrator
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET 74AHC123A; 74AHCT123A Dual retriggerable monostable multivibrator with reset Product sp...
Datasheet PDF File 74AHC123A PDF File

74AHC123A
74AHC123A

Overview
INTEGRATED CIRCUITS DATA SHEET 74AHC123A; 74AHCT123A Dual retriggerable monostable multivibrator with reset Product specification File under Integrated Circuits, IC06 2000 Mar 15 Philips Semiconductors Product specification Dual retriggerable monostable multivibrator with reset FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 °C and −40 to +125 °C • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long pulses up to 100% duty factor • Direct reset terminates output pulse • Output capability: standard (except for nREXT/CEXT).
DESCRIPTION The 74AHC/AHCT123A are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no.
7A.
The 74AHC/AHCT123A are dual retriggerable monostable multivibrators with output pulse width control by three methods.
The basic pulse time is programmed by selection of an external resistor (REXT) and capacitor (CEXT).
The external resistor and capacitor are normally connected as shown in Fig.
6.
74AHC123A; 74AHCT123A Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB).
By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired.
Alternatively an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering.
An internal connection from nRD to the input gate makes it possible to trigger the circuit by a positive-going signal at input nRD as shown in the function table.
Figs 8 and 9 illustrate pulse control by retriggering and early reset.
The basic...


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