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74ALVCH16501

NXP
Part Number 74ALVCH16501
Manufacturer NXP
Description 18-bit universal bus transceiver
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74ALVCH16501 18-bit universal bus transceiver (3-State) Product specification Supersedes data of 19...
Datasheet PDF File 74ALVCH16501 PDF File

74ALVCH16501
74ALVCH16501


Overview
INTEGRATED CIRCUITS 74ALVCH16501 18-bit universal bus transceiver (3-State) Product specification Supersedes data of 1998 Aug 31 IC24 Data Handbook 1998 Sep 29 Philips Semiconductors Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16501 FEATURES • Complies with JEDEC standard no.
8-1A.
• CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.
0 V • Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode.
DESCRIPTION The 74ALVCH16501 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is High.
When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level.
If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB.
When OEAB is High, the outputs are active.
When OEAB is Low, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
The output enables are complimentary (OEAB is active High, and OEBA is active Low).
To ensure the high impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
• All inputs have bushold circuitry • Output drive capability 50Ω transmission lines @ 85°C • 3-State non-inverting outputs for bus oriented applications QUICK REFERENCE DATA GND = 0V; Tamb = ...


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