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74ALVCH16543

NXP
Part Number 74ALVCH16543
Manufacturer NXP
Description 16-bit D-type registered transceiver
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET 74ALVCH16543 16-bit D-type registered transceiver; 3-state Product specification Superse...
Datasheet PDF File 74ALVCH16543 PDF File

74ALVCH16543
74ALVCH16543


Overview
INTEGRATED CIRCUITS DATA SHEET 74ALVCH16543 16-bit D-type registered transceiver; 3-state Product specification Supersedes data of 1998 Aug 31 File under Integrated Circuits, IC24 1999 Nov 23 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state FEATURES • In accordance with JEDEC standard no 8-1A • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTE™ flow-through pin-out architecture • 16-bit transceiver with D-type latch • Combines 16245 and 16373 type functions in one chip • Back-to-back registers for storage • Output drive capability 50 Ω transmission lines at 85 °C • Separate controls for data flow in each direction • All data inputs have bus hold • 3-state non-inverting outputs for bus oriented applications • Current drive ±24 mA at 3.
0 V.
DESCRIPTION The 74ALVCH16543 is a dual octal registered transceiver.
Each section contains two sets of D-type latches for temporary storage of the data flow in either direction.
FUNCTION TABLE See note 1.
INPUTS OUTPUTS nOEXX H X L L L L L L L Note 1.
XX = AB for A-to-B direction, BA for B-to-A direction; H = HIGH voltage level; L = LOW voltage level; nEXX X H ↑ ↑ L L L L L nLEXX X X L L ↑ ↑ L L H nBn, nAn X X h l h l H L X Z Z Z Z H L H L NC 74ALVCH16543 Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control in either direction of the data flow.
The ‘16543’ contains two sections each consisting of two sets of eight D-type latches with separate inputs and controls for each set.
For data flow from A to B, for example, the A-to-B enable (nEAB, where n equals 1 or 2) inputs must be LOW in order to enter data from nA0 to nA7, or take data from nB0 to nB7, as indicated in the function table.
With nEAB LOW, a LOW signal on the A-to-B latch enable (nLEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the nLEAB signal stores the A data into the latches...


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