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74ABT16373B

NXP
Part Number 74ABT16373B
Manufacturer NXP
Description 16-bit transparent latch
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) Product specification Supersedes data o...
Datasheet PDF File 74ABT16373B PDF File

74ABT16373B
74ABT16373B

Overview
INTEGRATED CIRCUITS 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) Product specification Supersedes data of 1995 Aug 03 IC23 Data Handbook 1998 Feb 27 Philips Semiconductors Philips Semiconductors Product specification 16-bit transparent latch (3-State) 74ABT16373B 74ABTH16373B FEATURES • 16-bit transparent latch • Multiple VCC and GND pins minimize switching noise • Power-up 3-State • Live insertion/extraction permitted • Power-up reset • 3-State output buffers • 74ABTH16373B incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs When nOE is Low, the latched or transparent data appears at the outputs.
When nOE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus.
Two options are available, 74ABT16373B which does not have the bus-hold feature and 74ABTH16373B which incorporates the bus-hold feature.
PIN CONFIGURATION 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1E 1D0 1D1 GND 1D2 1D3 VCC 1D4 1D5 GND 1D6 1D7 2D0 2D1 GND 2D2 2D3 VCC 2D4 2D5 GND 2D6 2D7 2E • Output capability: +64mA/–32mA • ICCL –19 mA maximum • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The 74ABT16373B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
The 74ABT16373B device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers.
The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates.
The data on each set of D inputs are transferred to the latch outputs when the Latch Enable (nE) input is High.
The latch remains transparent to the data inputs while nE is High, and stores the ...


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