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74AC373

STMicroelectronics
Part Number 74AC373
Manufacturer STMicroelectronics
Description OCTAL D-TYPE LATCH
Published Apr 3, 2005
Detailed Description 74AC373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s (OE). While the LE inputs is held at a hig...
Datasheet PDF File 74AC373 PDF File

74AC373
74AC373


Overview
74AC373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s (OE).
While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or s inversely.
When the LE is taken low, the Q outputs will be latched precisely or inversely at s the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in a normal logic DESCRIPTION state (high or low logic level) and while high level The AC373 is an advanced high-speed CMOS the outputs will be in a high impedance state.
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DataSheet4U.
com OCTAL D-TYPE LATCH with 3 STATE OUTPUT This device is designed to interface directly High NON INVERTING fabricated with sub-micron Speed CMOS systems with TTL and NMOS 2 silicon gate and double-layer metal wiring C MOS components.
technology.
It is ideal for low power applications All inputs and outputs are equipped with mantaining high speed operation similar to protection circuits against static discharge, giving equivalent Bipolar Schottky TTL.
them 2KV ESD immunity and transient excess These 8 bit D-Type latch are controlled by a latch voltage.
enable input (LE) and an output enable input s HIGH SPEED: tPD = 5 ns (TYP.
) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.
) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.
) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74AC373B 74AC373M PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 74AC373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND F UNCTIO N 3 State Output Enable Input (Active LOW) Data Inputs D0 to D7 3 State Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Suppl...


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