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IDT72261

Integrated Device Technology
Part Number IDT72261
Manufacturer Integrated Device Technology
Description CMOS SUPERSYNC FIFO
Published Apr 4, 2005
Detailed Description CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9 IDT72261 IDT72271 Integrated Device Technology, Inc. FEATURES: • • • • • ...
Datasheet PDF File IDT72261 PDF File

IDT72261
IDT72261

Overview
CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9 IDT72261 IDT72271 Integrated Device Technology, Inc.
FEATURES: • • • • • • • • • • • • • • • • 16,384 x 9-bit storage capacity (IDT72261) 32,768 x 9-bit storage capacity (IDT72271) 10ns read/write cycle time (8ns access time) Retransmit Capability Auto power down reduces power consumption Master Reset clears entire FIFO, Partial Reset clears data, but retains programmable settings Empty, Full and Half-full flags signal FIFO status Programmable Almost Empty and Almost Full flags, each flag can default to one of two preselected offsets Program partial flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Easily expandable in depth and width Independent read and write clocks (permit simultaneous reading and writing with one clock signal Available in the 64-pin Thin Quad Flat Pack (TQFP), 64pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin Pin Grid Array (PGA) Output enable puts data outputs into high impedance High-performance submicron CMOS technology Industrial temperature range (-40OC to +85OC) is available, tested to military electrical specifications DESCRIPTION: The IDT72261/72271 are monolithic, CMOS, high capacity, high speed, low power first-in, first-out (FIFO) memories with clocked read and write controls.
These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, local area networks (LANs), and interprocessor communication.
Both FIFOs have a 9-bit input port (Dn) and a 9-bit output port (Qn).
The input port is controlled by a free-running clock (WCLK) and a data input enable pin (WEN).
Data is written into the synchronous FIFO on every clock when WEN is asserted.
The output port is controlled by another clock pin (RCLK) and enable pin (REN).
The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronously for dual clock ...


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