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IDT723622

Integrated Device Technology
Part Number IDT723622
Manufacturer Integrated Device Technology
Description CMOS Bidirectional SyncFIFO memory
Published Apr 4, 2005
Detailed Description CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 Integrated Device Technology, Inc. IDT723622 IDT723632 IDT72...
Datasheet PDF File IDT723622 PDF File

IDT723622
IDT723622


Overview
CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 Integrated Device Technology, Inc.
IDT723622 IDT723632 IDT723642 FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs buffering data in opposite directions • Memory storage capacity: IDT723622–256 x 36 x 2 IDT723632–512 x 36 x 2 IDT723642–1024 x 36 x 2 • Mailbox bypass register for each FIFO • Programmable Almost-Full and Almost-Empty flags • Microprocessor Interface Control Logic • IRA, ORA, AEA, and AFA flags synchronized by CLKA • IRB, ORB, AEB, and AFB flags synchronized by CLKB • Supports clock frequencies up to 67MHz • Fast access times of 11ns • Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving 120-pin Thin Quad Flatpack (PF) • Low-power 0.
8-Micron Advanced CMOS technology • Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications DESCRIPTION: The IDT723622/723632/723642 is a monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memory which supports clock frequencies up to 67MHz and have read access times as fast as 11ns.
Two independent 256/512/ 1024x36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions.
Each FIFO has flags to indicate empty and full conditions and two programable flags (almost FUNCTIONAL BLOCK DIAGRAM CLKA MBF1 Mail 1 Register 256 x 36 512 x 36 1024 x 36 SRAM Input Register Output Register W/RA ENA MBA CSA Port-A Control Logic RST1 FIFO1, Mail1 Reset Logic 36 36 Write Pointer Read Pointer Status Flag Logic ORB AFA FS0 FS1 A0 - A35 IRA FIFO 1 AEB Programmable Flag Offset Registers 9 FIFO 2 B0 - B35 ORA AEA 36 Status Flag Logic Write Pointer 36 IRB AFB FIFO2, Mail2 Reset Logic Read Pointer RST2 Output Register 256 x 36 512 x 36 1024 x 36 SRAM Mail 2 Register Input Register Port-B Control Logic CLKB CSB W/RB ENB MBB M...



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