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SAA7215

NXP
Part Number SAA7215
Manufacturer NXP
Description Integrated MPEG AVGD decoders
Published Apr 8, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET SAA7215; SAA7216; SAA7221 Integrated MPEG AVGD decoders Preliminary specification Supers...
Datasheet PDF File SAA7215 PDF File

SAA7215
SAA7215


Overview
INTEGRATED CIRCUITS DATA SHEET SAA7215; SAA7216; SAA7221 Integrated MPEG AVGD decoders Preliminary specification Supersedes data of 1998 Sep 11 File under Integrated Circuits, IC02 2000 Jan 31 Philips Semiconductors Preliminary specification Integrated MPEG AVGD decoders FEATURES General features • Integrated MPEG AVGD decoder: audio, video and graphics decoding and digital video encoding • 5 planes display chain: background colour, background plane, MPEG display plane, graphics plane and cursor plane • 16-Mbit or 32-Mbit external Synchronous DRAM (SDRAM) for MPEG audio and video decoding and graphics data storage • Single or double external SDRAM organized as 1 M × 16 or 2 × 1 M × 16 (two independent 16-bit data bus) interfacing at 81 MHz.
Due to efficient memory use in MPEG decoding, more than 1 Mbit is available for graphics in the single SDRAM configuration whereas 17 Mbits are available in the double SDRAM configuration.
• All basic operations of the AVGD decoder are possible in both 16- and 32-Mbit configuration; enhanced performance is achieved by the use of 32-Mbit external SDRAM • Targeted to BSkyB 3.
0 and Canal+ basic box and web box specifications • Fast 16-bit data + 22-bit address synchronous or asynchronous interface with external controller at up to 40.
5 MHz • Dedicated input for compressed audio and video in Packetized Elementary Stream (PES) or Elementary Stream (ES) in byte wide or bit serial format.
Accompanying strobe signals distinguish between audio and video data.
Transport stream error correction available.
• Audio and/or video can also be input via the CPU interface in PES or ES in 8 or 16-bit parallel format • Single 27 or 40.
5 MHz external clock for time base reference and internal processing.
Internal system time base at 90 kHz can be synchronized via CPU port.
All required decoding and presentation clocks are generated internally.
• Flexible memory allocation under control of the external CPU enables optimized partitioning of memory f...


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