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IDT72V36110

Part Number	IDT72V36110
Manufacturer	Integrated Device Tech
Description	CMOS FIFO memories
Published	Apr 21, 2005
Detailed Description	3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO 65,536 x 36 131,072 x 36 IDT72V36100 IDT72V36110 FEATURES: • Choose am...
Datasheet	IDT72V36110 PDF File

Overview

3.
3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO 65,536 x 36 131,072 x 36 IDT72V36100 IDT72V36110 FEATURES: • Choose among the following memory organizations: IDT72V36100 ⎯ 65,536 x 36 IDT72V36110 ⎯ 131,072 x 36 • Higher density, 2Meg and 4Meg SuperSync II FIFOs • Up to 166 MHz Operation of the Clocks • User selectable Asynchronous read and/or write ports (PBGA Only) • User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out • Big-Endian/Little-Endian user selectable byte representation • 5V input tolerant • Fixed, low first word latency • Zero latency retransmit • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings FUNCTIONAL BLOCK DIAGRAM *Available on the PBGA package only.
• Empty, Full and Half-Full flags signal FIFO status • Programmable Almost-Empty and Almost...

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