DatasheetsPDF.com

IDT72V36104

Part Number	IDT72V36104
Manufacturer	Integrated Device Technology
Description	3.3 VOLT CMOS SyncBiFIFO
Published	Jun 26, 2011
Detailed Description	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2 IDT72V3684 32,768 x 36 x 2 IDT72V3694 65,536 x 36 x 2 IDT72...
Datasheet	IDT72V36104 PDF File

Overview

3.
3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2 IDT72V3684 32,768 x 36 x 2 IDT72V3694 65,536 x 36 x 2 IDT72V36104 FEATURES • • • • • • • • • • • • Memory storage capacity: IDT72V3684 – 16,384 x 36 x 2 IDT72V3694 – 32,768 x 36 x 2 IDT72V36104 – 65,536 x 36 x 2 Clock frequencies up to 100 MHz (6.
5ns access time) Two independent clocked FIFOs buffering data in opposite directions Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRB flag functions) Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024 ) Serial or parallel programming of partial flags Retransmit Capability • • • • Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte) Big- or Little-Endian format for word and byte bus sizes Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Auto power down minimizes power dissipation Available in space saving 128-pin Thin Quad Flatpack (TQFP) Pin compatible to the lower density parts, IDT72V3624/72V3634/ 72V3644/72V3654/72V3664/72V3674 Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register Output BusMatching Input Register 36 RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 36 Output Register CLKA CSA W/RA ENA MBA MRS1 PRS1 Port-A Control Logic 36 FIFO1, Mail1 Reset Logic 36 Write Pointer Read Pointer Status Flag Logic EFB/ORB AEB FFA/IRA AFA FS2 FS0/SD FS1/SEN A0-A35 EFA/ORA AEA FIFO1 Programmable Flag Offset Registers 16 FIFO2 Timing Mode FWFT B0-B35 Status Flag Logic Read Pointer Write Pointer 36 FFB/IRB AFB 36 RT1 RTM RT2 Output Register Input BusMatching 36 16,384 x 36 32,768 x 36 65,536 x ...

Similar Datasheet

IDT72V36100 CMOS FIFO - Integrated Device Tech
IDT72V36100 3.3 VOLT HIGH-DENSITY SUPERSYNC FIFO - Renesas
IDT72V36102 3.3 VOLT CMOS SyncBiFIFO - Integrated Device Technology
IDT72V36103 3.3 VOLT CMOS SyncFIFO - Integrated Device Technology
IDT72V36104 3.3 VOLT CMOS SyncBiFIFO - Integrated Device Technology
IDT72V36106 3.3 VOLT CMOS TRIPLE BUS SyncFIFO - Integrated Device Technology
IDT72V3611 CMOS FIFO memories - IDT
IDT72V36110 CMOS FIFO memories - Integrated Device Tech
IDT72V36110 3.3 VOLT HIGH-DENSITY SUPERSYNC FIFO - Renesas
IDT72V3612 CMOS FIFO memories - IDT

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)