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74HCT192

Philips
Part Number 74HCT192
Manufacturer Philips
Description Presettable synchronous BCD decade up/down counter
Published Apr 23, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Fam...
Datasheet PDF File 74HCT192 PDF File

74HCT192
74HCT192

Overview
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT192 Presettable synchronous BCD decade up/down counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter FEATURES • Synchronous reversible counting • Asynchronous parallel load • Asynchronous reset • Expandable without external logic • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT192 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no.
7A.
The 74HC/HCT192 are synchronous BCD up/down counters.
Separate up/down clocks, CPU and CPD respectively, simplify operation.
The outputs change state synchronously with the LOW-to-HIGH transition of either clock input.
If the CPU clock is pulsed while CPD is held HIGH, the device will count up.
If the CPD clock is pulsed while CPU is held HIGH, the device will count down.
Only one clock input can be held HIGH at any time, or erroneous operation will result.
The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL).
The “192” contains four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions.
Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CPD input will decrease the count by one, while a similar transition on the CPU input will advance the count by one.
74HC/HCT192 One clock should be held HIGH while counting with the other, otherwise the circuit will either count b...


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