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LS7061

Part Number	LS7061
Manufacturer	LSI Computer Systems
Description	32 BIT/DUAL 16 BIT BINARY UP COUNTER WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
Published	Apr 25, 2005
Detailed Description	LSI/CSI UL ® LS7061/7063 (631) 271-0400 FAX (631) 271-0405 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville...
Datasheet	LS7061 PDF File

Overview

LSI/CSI UL ® LS7061/7063 (631) 271-0400 FAX (631) 271-0405 LSI Computer Systems, Inc.
1235 Walt Whitman Road, Melville, NY 11747 A3800 Aug.
1998 32 BIT/DUAL 16 BIT BINARY UP COUNTER WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS FEATURES: • DC to 15 MHz Count Frequency • Byte Multiplexer • DC to 1 MHz Scan Frequency • +4.
75V to +5.
25V Operation (VDD-VSS) • Latch Provided for External High Speed Counter Byte, Effectively Extending Count Frequency to 3.
84GHz • Three-State Data Outputs, Bus and TTL Compatible • Inputs TTL and CMOS Compatible • Unique Cascade Feature Allows Multiplexing of Successive Bytes of Data in Sequence in Multiple Counter Systems • LS7061, LS7063 (DIP); LS7061-S, LS7063-S (SOIC) (See Figures 1 & 2) DESCRIPTION: The LS7061/LS7063 is a monolithic, ion implanted MOS Silicon Gate, 32 bit/dual 16 bit up counter.
The IC includes 40 latches, multiplexer, eight three-state binary data output drivers and output cascading logic.
DESCRIPTION OF OPERATION: 32 (16) BIT BINARY UP COUNTER - LS7061 (LS7063) The 32 (16) bit static ripple through counter increments on the negative edge of the input count pulse.
Maximum ripple time is 4µs (2µs) - transition count of 32 (16) ones to 32 (16) zeros.
Guaranteed count frequency is DC to 15MHz.
See Figure 8A (8B) for Block Diagram.
COUNT - LS7061, COUNT A - LS7063 Input count pulses to the 32 (first 16) bit counter may be applied through this input.
This input is the most significant bit of the external data byte.
COUNT B - LS7063 Count pulses may be applied to the last 16 bits of the binary counter through this input.
The counter advances on the negative transition of these pulses.
RESET All 32 counter bits are reset to zero when RESET is brought low for a minimum of 1µs.
RESET must be high for a minimum of 300ns before next valid count can be recorded.
COUNT B must be held low when RESET is brought low to ensure proper reset of Counter B for LS7063.
TEST COUNT - LS7061 Count pulses may be applied to the last 16 bits of ...

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