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MC100EP139

ON Semiconductor
Part Number MC100EP139
Manufacturer ON Semiconductor
Description Clock Generation Chip
Published Apr 26, 2005
Detailed Description MC10EP139, MC100EP139 3.3 V / 5 V ECL ÷2/4, ÷4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷...
Datasheet PDF File MC100EP139 PDF File

MC100EP139
MC100EP139

Overview
MC10EP139, MC100EP139 3.
3 V / 5 V ECL ÷2/4, ÷4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications.
The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.
The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state.
This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control.
The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random state; therefore the master reset (MR) input may require assertion to ensure system synchronization.
Int...


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