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MC10EP116

ON Semiconductor
Part Number MC10EP116
Manufacturer ON Semiconductor
Description Hex Differential Line Receiver
Published Apr 26, 2005
Detailed Description MC10EP116 Hex Differential Line Receiver The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 ...
Datasheet PDF File MC10EP116 PDF File

MC10EP116
MC10EP116


Overview
MC10EP116 Hex Differential Line Receiver The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device.
The 3.
0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.
A VBB pin is available to AC couple an input signal to the device.
More information on AC coupling can be found in the design handbook interfacing with ECLinPS on our website.
The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state.
Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device.
Note that the input clamp will take affect only if both inputs fall 2.
5V below VCC.
All VCC and VEE pins must be externally connected to power supply to guarantee proper operation.
http://onsemi.
com 32–LEAD TQFP FA SUFFIX CASE 873A MARKING DIAGRAM* • • • • • • • • • • • • 230ps Typical Propagation Delay High Bandwidth to 3.
0 GHz Typical PECL mode: 3.
0V to 5.
5V VCC with VEE = 0V ECL mode: 0V VCC with VEE = –3.
0V to –5.
5V Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D Q Output will default LOW with inputs open or at VEE ESD Protection: 2KV HBM, 100V MM VBB Output New Differential Input Common Mode Range Moisture Sensitivity Level 2 For Additional Information, See Application Note AND8003/D Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 Transistor Count: 729 devices LOGIC DIAGRAM D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 VBB Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 MC10 EP116 AWLYYWW 32 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D PIN DESCRIPTION PIN D[0:5], D[0:5] Q[0:5], Q[0:5] VBB VCC VEE FUNCTION ECL Differential Data Inputs ECL Differe...



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