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MCM67M618A

Motorola
Part Number MCM67M618A
Manufacturer Motorola
Description 64K x 18 Bit BurstRAM Synchronous Fast Static RAM
Published Apr 30, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67M618A/D Product Preview MCM67M618A 64K x 18 Bit B...
Datasheet PDF File MCM67M618A PDF File

MCM67M618A
MCM67M618A

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67M618A/D Product Preview MCM67M618A 64K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67M618A is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the MC68040 and PowerPC™ microprocessors.
It is organized as 65,536 words of 18 bits, fabricated using Motorola’s high–performance silicon–gate BiCMOS technology.
The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications.
Synchronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control signals, except output enable (G), are clock (K) controlled through positive–edge– triggered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP) or transfer start cache controller (TSC) input pins.
Subsequent burst addresses are generated internally by the MCM67M618A (burst sequence imitates that of the MC68040) and controlled by the burst address advance (BAA) input pin.
The following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input.
This feature eliminates complex off–chip write pulse generation and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable bytes.
LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus widths and cache memory.
• • • • • • • • • • Single 5 V ± 5% Power Supply Fast...


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