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MCM67M618B

Motorola
Part Number MCM67M618B
Manufacturer Motorola
Description 64K x 18 Bit BurstRAM Synchronous Fast Static RAM
Published Apr 30, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67M618B/D Advance Information MCM67M618B 64K x 18 B...
Datasheet PDF File MCM67M618B PDF File

MCM67M618B
MCM67M618B

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67M618B/D Advance Information MCM67M618B 64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67M618B is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the MC68040 and PowerPC™ microprocessors.
It is organized as 65,536 words of 18 bits, fabricated using Motorola’s high–performance silicon–gate BiCMOS technology.
The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications.
Synchronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control sigDQ9 nals, except output enable (G), are clock (K) controlled through posiDQ10 VCC tive–edge–triggered noninverting registers.
VSS Bursts can be initiated with either transfer start processor (TSP) or DQ11 transfer start cache controller (TSC) input pins.
Subsequent burst DQ12 addresses are generated internally by the MCM67M618B (burst DQ13 sequence imitates that of the MC68040) and controlled by the burst DQ14 address advance (BAA) input pin.
The following pages provide more VSS detailed information on burst controls.
VCC Write cycles are internally self–timed and are initiated by the rising DQ15 edge of the clock (K) input.
This feature eliminates complex off–chip DQ16 write pulse generation and provides increased flexibility for incoming DQ17 signals.
Dual write enables (LW and UW) are provided to allow individually writeable bytes.
LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus widths and cache...


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