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NJU3555

New Japan Radio
Part Number NJU3555
Manufacturer New Japan Radio
Description 4-BIT SINGLE CHIP OTP MICRO CONTROLLER
Published May 7, 2005
Detailed Description NJU3555 PRELIMINARY 4-BIT SINGLE CHIP OTP MICRO CONTROLLER s GENERAL DESCRIPTION The NJU3555 is the C-MOS 4-bit Single ...
Datasheet PDF File NJU3555 PDF File

NJU3555
NJU3555


Overview
NJU3555 PRELIMINARY 4-BIT SINGLE CHIP OTP MICRO CONTROLLER s GENERAL DESCRIPTION The NJU3555 is the C-MOS 4-bit Single Chip OTP type Micro Controller with programmable Flash Memory.
It is completely compatible with the NJU3505 in function and the pin configuration.
Therefore, the NJU3555 is suitable for the final evaluation before NJU3505 mask generation, the small quantity production and short leadtime.
* In this data sheet, only OTP programming and the difference between NJU3555 and NJU3505 are mentioned mainly.
Therefore the detail function and specification should be referred on the NJU3505 data sheet.
NJU3555FA1 NJU3555L s PACKAGE OUTLINE s FEATURES q q q q q 8,192 X 8bits 8,128 X 8bits (Program area) 64 X 8bits (Option area) Internal Data RAM 256 X 4bits Wide operating voltage range 2.
7V ~ 5.
5V Package outline QFP44-A1 / SDIP42 (Compatible with NJU3505) ROM programmer “SUPERPRO/L” by XELTEK co,.
Internal One Time Programmable ROM s PIN CONFIGURATION IN OTP PROGRAMMING MODE [ QFP44-A1 ] CNT2 Open CNT1 Open D7 D6 [ SDIP42 ] CNT1 CNT2 VDD Open D5 D4 D3 D2 Open D1 D0 Open Open RESET PROM CLK REQ VSS VSS Open 1 2 Open 3 4 5 6 RESET PROM CLK REQ VSS 7 8 9 10 12 13 14 15 16 17 18 19 20 21 11 33 32 31 30 29 28 27 26 25 24 22 23 NJU3555FA1 Open VDD Open VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Open D7 D6 VDD Open D5 D4 D3 D2 Open D1 D0 44 43 42 41 40 39 38 37 36 35 34 NJU3555L Open Note) The pin configuration in Normal operating mode is the same as NJU3505.
VSS -1- NJU3555 s BLOCK DIAGRAM -2NJU3555 Interrupt CPU CORE Logic VDD VSS INT1 EXTI/PK0 INT2 TIMER1 STACK X Reg Y Reg AC TEST RESET INT3 CNTI/PK1 TIMER2 X’ Reg MUX Y’ Reg TLU addr PC INT4 SDO/PL0 PRESCALER SDI(O)/PL1 SIO OTP ROM ALU 8192 x 8 bits OSC1 SCK/CKOUT AIN0/PI0 CPU TIMING GENERATOR OSC OSC2 AIN1/PI1 AIN2/PI2 AIN3/PI3 IR RAM 256 x 4 bits ID STANDBY CONTROLLER AIN4/PA0 ...



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