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MMBFJ177LT1

Motorola
Part Number MMBFJ177LT1
Manufacturer Motorola
Description JFET Chopper
Published May 9, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MMBFJ177LT1/D JFET Chopper P–Channel — Depletion 3 GATE...
Datasheet PDF File MMBFJ177LT1 PDF File

MMBFJ177LT1
MMBFJ177LT1

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MMBFJ177LT1/D JFET Chopper P–Channel — Depletion 3 GATE 2 SOURCE MMBFJ177LT1 1 DRAIN 3 1 MAXIMUM RATINGS Rating Drain–Gate Voltage Reverse Gate–Source Voltage Symbol VDG VGS(r) Value 25 – 25 Unit Vdc Vdc 2 CASE 318 – 08, STYLE 10 SOT– 23 (TO – 236AB) THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR– 5 Board(1) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature Symbol PD Max 225 1.
8 RqJA TJ, Tstg 556 – 55 to +150 Unit mW mW/°C °C/W °C DEVICE MARKING MMBFJ177LT1 = 6Y ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS Gate–Source Breakdown Voltage (VDS = 0, ID = 1.
0 µAdc) Gate Reverse Current (VDS = 0 Vdc, VGS = 20 Vdc) Gate Source Cutoff Voltage (VDS = 15 Vdc, ID = 10 nAdc) V(BR)GSS IGSS VGS(off) 30 — 0.
8 — 1.
0 2.
5 Vdc nAdc Vdc ON CHARACTERISTICS Zero–Gate–Voltage Drain Current(2) (VGS = 0, VDS = 15 Vdc) Drain Cutoff Current (VDS = 15 Vdc, VGS = 10 Vdc) Drain Source On Resistance (ID = 500 µAdc) Input Capacitance Reverse Transfer Capacitance VDS = 0, , VGS = 10 Vdc f = 1.
0 MHz IDSS ID(off) rDS(on) Ciss Crss 1.
5 — — — — 20 1.
0 300 11 5.
5 mAdc nAdc Ω pF 1.
FR– 5 = 1.
0 0.
75 0.
062 in.
2.
Pulse Test: Pulse Width < 300 µs, Duty Cycle ≤ 2%.
  Thermal Clad is a trademark of the Bergquist Company Motorola Small–Signal Transistors, FETs and Diodes Device Data © Motorola, Inc.
1997 1 MMBFJ177LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design.
The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package.
With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.
037 0.
95 0.
037 0.
95 0.
079 2.
0 0...


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