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PM8353

PMC-Sierra
Part Number PM8353
Manufacturer PMC-Sierra
Description 4-Channel 1.0-1.25 Gbps Transceiver
Published May 9, 2005
Detailed Description PMC-Sierra,Inc. PM8353 QuadPHY™ 4-Channel 1.0-1.25 Gbps Transceiver FEATURES • Four independent 1.0-1.25 Gbit/s transc...
Datasheet PDF File PM8353 PDF File

PM8353
PM8353

Overview
PMC-Sierra,Inc.
PM8353 QuadPHY™ 4-Channel 1.
0-1.
25 Gbps Transceiver FEATURES • Four independent 1.
0-1.
25 Gbit/s transceivers • Four secondary channels to support channel redundancy • Ultra low power operation: 1.
25 Watt typical • Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic • Physical Coding Sublayer (PCS) logic for Gigabit Ethernet • Selectable 8-bit, 10-bit, or IEEE 802.
3z GMII parallel interface • Optional Receive FIFOs which synchronize incoming data to local clock domain • “Trunking” feature to de-skew and align received parallel data across four channels • 100-156 MHz Single Data Rate (SDR) parallel transmit interface with clock forwarding • 100-125 MHz SDR parallel receive interface • Extensive control of loopback, BIST, and operating modes via 802.
3 compliant MDC/MDIO serial interface • Built-in packet generator/checker • IEEE 1149.
1 JTAG testing support • IEEE 802.
3z Gigabit Ethernet and ANSI X3T11 Fibre Channel support • High speed outputs which feature programmable output current to directly drive dual-terminated line • 2.
5V, 0.
25 micron CMOS technology with 3.
3V tolerant I/O • Direct interface to optical modules, coax, or serial backplanes • Small footprint 19x19 mm, 289-pin PBGA requirements) which produces run length limited data streams for serial transmission.
A receive FIFO optionally aligns all incoming parallel data to the local clock domain, adding or removing IDLE sequences as required.
This simplifies implementation of the upstream ASIC by removing the requirement to deal with multiple clock domains.
When trunking is enabled, the QuadPHY can remove cable skew differences equivalent to several meters, presenting 4-byte data vectors at the receive interface exactly as they were transmitted.
APPLICATIONS • • • • • High speed serial backplanes Gigabit Ethernet links Fibre Channel links Intra-system interconnect ASIC to PMD link EXAMPLE ARCHITECTURE GENERAL DESCRIPTION The is a Quad PHYsical...


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