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PM8372

PMC-Sierra
Part Number PM8372
Manufacturer PMC-Sierra
Description 4-Port FC/GE Retimer and FC-AL Port Bypass Controller
Published Apr 27, 2009
Detailed Description PM8372 PBC 4x2G Preview 4-Port FC/GE Retimer and FC-AL Port Bypass Controller GENERAL • Supports 4 Fibre Channel Physic...
Datasheet PDF File PM8372 PDF File

PM8372
PM8372

Overview
PM8372 PBC 4x2G Preview 4-Port FC/GE Retimer and FC-AL Port Bypass Controller GENERAL • Supports 4 Fibre Channel Physical Interfaces at 1.
0625 or 2.
125 Gbit/s per Fibre Channel – Physical Interface www.
datasheet4u.
com (FC-PI) or 4 Gigabit Ethernet Retimers at 1.
25 Gbit/s per IEEE 802.
3z.
• Each port supports FC 1G or 2G rate detection/auto-selection.
• Supports Arbitrated Loop and Retimer configuration.
• Each port is independently selectable to perform retimer, reclocker or bypass-path function.
• Non-blocking crossconnect supports protection switching, broadcasting and multicasting.
• Automatic selection of retimer, reclocker or bypass-path function to minimize latency and jitter when a disk is bypassed.
• Per-port receive monitoring for loss of signal, error rate, and link level violations.
• Supports single-ended or differential 106.
25 MHz reference clock REFCLK for Fibre Channel applications or 125 Mhz reference clock for Gigabit Ethernet applications.
TEST AND CONTROL • Supports optional 2-pin serial management interface using selectable Two-Wire Interface (TWI) or MDC/MDIO protocol for configuration and diagnostic access.
• For normal mode of operation, a management interface is not required.
• Digital Loss of Link (DLOLB) detect outputs for monitoring individual or multiple links.
DLOLB can be programmed to indicate excessive 8B/10B code error rate, loss of synchronization, loss of signal, CRC32 errors, or comma density.
• Interrupt output to flag changes in bypass state and DLOLB error conditions.
• Supports built-in self-test (BIST) via internal Fibre Channel pattern generation and checking.
• External control pins can be overwritten by registers.
HIGH-SPEED INTERFACE • High-speed outputs with selectable preemphasis per port to counteract dielectric losses and allow maximum reach on printed circuit boards.
• Selectable receive input equalization for improved signal integrity.
• Minimized board footprint and improved signal integrity achieved because: • ...


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