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M74HC00 Datasheet PDF

Mitsubishi
Part Number M74HC00
Manufacturer Mitsubishi
Title Quad 2 Input NAND Gate
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File Size 429.51KB
Datasheet PDF File M74HC00 PDF File


M74HC00 M74HC00 M74HC00




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M74HC00 : The M74HC00 is an high speed CMOS QUAD 2-INPUT NAND GATE fabricated with silicon gate C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/8 M74HC00 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L L H H B L H L H Y H H H L ABSOLUTE MAXIMUM RATINGS Sy.

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M74HC02 : The M74HC02 is an high speed CMOS QUAD 2-INPUT NOR GATE fabricated with silicon gate C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/8 M74HC02 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 2, 5, 8, 11 3, 6, 9, 12 1, 4, 10, 13 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L L H H B L H L H Y H L L L ABSOLUTE MAXIMUM RATINGS Sym.

M74HC03 : The M74HC03 is an high speed CMOS QUAD 2-INPUT OPEN DRAIN NAND GATE fabricated with silicon gate C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. This device can, with an external pull-up resistor, be used in wired AND configuration. This device can be also used as a led driver and in any other application requiring a current sink. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/8 M74HC03 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBO.

M74HC04 : The M74HC04 is a high-speed CMOS hex inverter manufactured using silicon gate C2MOS technology. The internal circuit is composed of 3 stages including a buffer output which enables high noise immunity and stable output. All inputs are equipped with protection circuits to guard against static discharge and transient excess voltage. Order code Table 1. Device summary Temperature range Package Packaging Marking M74HC04B1R M74HC04YRM13TR(1) M74HC04RM13TR M74HC04TTR M74HC04YTTR(1) -55 °C to +125 °C -40 °C to +125 °C -55 °C to +125 °C -55 °C to +125 °C -40 °C to +125 °C DIP14 Tube M74HC04B1 SO14 (automotive grade) Tape and reel 74HC04Y SO14 Tape and reel 74HC04 TSSOP14 Tape and ree.

M74HC05 : The M74HC05 is an high speed CMOS HEX INVERTER (OPEN DRAIN) fabricated with silicon gate C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/8 M74HC05 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 5, 9, 11, 13 2, 4, 6, 8, 10, 12 7 14 SYMBOL 1A to 6A 1Y to 6Y GND VCC NAME AND FUNCTION Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L H Z : High Impedance Y Z L ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO .

M74HC07 : The M74HC07 is an high speed CMOS HEX OPEN DRAIN BUFFER fabricated with silicon gate C2MOS technology. The internal circuit is composed of 2 stages including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS May 2003 1/10 M74HC07 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 5, 9, 11, 13 2, 4, 6, 8, 10, 12 7 14 SYMBOL 1A to 6A 1Y to 6Y GND VCC NAME AND FUNCTION Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L H Z : High Impedance Y L Z ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK .

M74HC08 : The M74HC08 is a high-speed CMOS quad dualinput and gate fabricated with silicon gate C2MOS technology. The internal circuit is composed of two stages including a buffer output which enables high noise immunity and stable output. All inputs are equipped with protection circuits to guard against static discharge and transient excess voltage. Table 1: Device summary Order code M74HC08YRM13TR(1) Temperature range -40 °C to +125 °C M74HC08RM13TR M74HC08TTR M74HC08YTTR1 -55 °C to +125 °C -55 °C to +125 °C -40 °C to +125 °C Package SO14 (automotive grade)1 SO14 TSSOP14 TSSOP14 (automotive grade)1 Packaging Marking Tape and 74HC08Y reel Tape and reel Tape and reel Tape and reel 74HC08 HC0.

M74HC09 : The M74HC09 is an high speed CMOS QUAD 2-INPUT OPEN DRAIN AND GATE fabricated with silicon gate C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/8 M74HC09 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L L H H Z : High Impedance B L H L H Y L L.

M74HC10 : The M74HC10 is an high speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/8 M74HC10 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 9 2, 4, 10 13, 5, 11 12, 6, 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L X X H X : Don‘t Care B X L X H .

M74HC107 : bsThe M74HC107 is an high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate OC2MOS technology. These flip-flop are edge -sensitive to the clock input and change state on t(s)the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC107B1R M74HC107M1R T&R M74HC107RM13TR M74HC107TTR CLEAR input and Q and Q outputs. CLEAR is independent of the clock and accomplished by a logic low on the input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. Obsolete ProducPIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC107 INPUT A.

M74HC109 : The M54/74HC109 is a high speed CMOS DUAL JK FLIP-FLOP WITH PRESET AND CLEAR fabri2 cated in silicon gate C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. In accordance with the logic level on the J and K input is device changes state on positive going transitions of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection December 1992 1/11 M54/M74HC109 PIN DES.

M74HC11 : The M74HC11 is an high speed CMOS TRIPLE 3-INPUT AND GATE fabricated with silicon gate C2MOS technology. The internal circuit is composed of 4 stages including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/8 M74HC11 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 3, 9 2, 4, 10 13, 5, 11 12, 6, 8 7 14 SYMBOL 1A to 3A 1B to 3B 1C to 3C 1Y to 3Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE A L X X H X : Don’t Care B X L X H.

M74HC112 : The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54HC112/M74HC112 dual JK flip-flop features individual J,K, clock, and asynchronous set and clearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped withprotection .

M74HC113 : The M54/74HC113 is a high speed CMOS DUAL JK FLIP FLOP WITH PRESET fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This circuit offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will function as shown in the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. All inputs are equ.

M74HC123 : The M54/74HC123 is a high speed CMOS MONOSTABLE multivibrator fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. There are two trigger inputs, A INPUT (negative edge) and 8 INPUT (positive edge). These inputs are valid for slow rising/falling signals, (tr = tf = I sec). The device may also be triggered by using the CLR input (positive-edge) because of the Schmitt-trigger input ; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor Rx and capacitor Cx. When Cx ≥ 10nF and Rx ≥ 10KΩ, the output pulse width value is approssim.




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