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74HC237

Part Number	74HC237
Manufacturer	Philips
Description	3-to-8 line decoder/demultiplexer
Published	May 28, 2005
Detailed Description	INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Fam...
Datasheet	74HC237 PDF File

Overview

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT237 3-to-8 line decoder/demultiplexer with address latches Product speciﬁcation File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product speciﬁcation 3-to-8 line decoder/demultiplexer with address latches FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or independent controls • Active HIGH mutually exclusive outputs • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no.
7A.
74HC/HCT237 The 74HC/HCT237 are 3-to-8 line decoder/demultiplexers with latches at the three address inputs (An).
The “237” essentially combines the 3-to-8 decoder function with a 3-bit storage latch.
When the latch is enabled (LE = LOW), the “237” acts as a 3-to-8 active LOW decoder.
When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches.
Further address changes are ignored as long as LE remains HIGH.
The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation.
All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The “237” is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL / tPLH PARAMETER propagation delay An to Yn LE to Yn E1 to Yn E2 to Yn CI CPD Notes 1.
CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: ...

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