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BB501

Hitachi
Part Number BB501
Manufacturer Hitachi
Description Build in Biasing Circuit MOS FET IC UHF/VHF RF Amplifier
Published Jun 3, 2005
Detailed Description BB501C Build in Biasing Circuit MOS FET IC UHF RF Amplifier ADE-208-701C (Z) 4th. Edition Nov. 1998 Features • Build in...
Datasheet PDF File BB501 PDF File

BB501
BB501

Overview
BB501C Build in Biasing Circuit MOS FET IC UHF RF Amplifier ADE-208-701C (Z) 4th.
Edition Nov.
1998 Features • Build in Biasing Circuit; To reduce using parts cost & PC board space.
• High gain; PG = 21.
5 dB typ.
at f = 900 MHz • Low noise; NF = 1.
85 dB typ.
at f = 900 MHz • Withstanding to ESD; Build in ESD absorbing diode.
Withstand up to 200V at C=200pF, Rs=0 conditions.
• Provide mini mold packages; CMPAK-4(SOT-343mod) Outline CMPAK-4 2 3 1 4 1.
Source 2.
Gate1 3.
Gate2 4.
Drain Notes: 1.
Marking is “AS–”.
2.
BB501C is individual type number of HITACHI BBFET.
BB501C Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Drain current Channel power dissipation Channel temperature Storage temperature Symbol VDS VG1S VG2S ID Pch Tch Tstg Ratings 6 +6 –0 +6 –0 20 100 150 –55 to +150 Unit V V V mA mW °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS Min 6 +6 +6 — — 0.
5 0.
5 7 19 Typ — — — — — 0.
7 0.
7 10 24 Max — — — +100 +100 1.
0 1.
0 13 29 Unit V V V nA nA V V mA mS Test Conditions I D = 200µA VG1S = VG2S = 0 I G1 = +10 µA VG2S = VDS = 0 I G2 = +10 µA VG1S = VDS = 0 VG1S = +5V VG2S = VDS = 0 VG2S = +5V VG1S = VDS = 0 VDS = 5V, VG2S = 4V I D = 100µA VDS = 5V, VG1S = 5V I D = 100µA VDS = 5V, VG1 = 5V VG2S = 4V, RG = 47kΩ VDS = 5V, VG1 = 5V VG2S =4V RG = 47kΩ, f = 1kHz VDS = 5V, VG1 = 5V VG2S =4V, RG = 47kΩ f = 1MHz VDS = 5V, VG1 = 5V VG2S =4V, RG = 47kΩ Noise figure NF — 1.
85 2.
4 dB f = 900MHz Gate1 to source cutoff current I G1SS Gate2 to source cutoff current I G2SS Gate1 to source cutoff voltage VG1S(off) Gate2 to source cutoff voltage VG2S(off) Drain current Forward transfer admittance I D(op) |yfs| Input capacitance Output capacitance c iss c oss 1.
4 0.
7 — 17 1.
7 1.
1 0.
019 21.
5 2.
0 1.
5 0.
04 — pF pF pF dB Reverse transfer capacitance c rss Power gain PG 2 ...


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