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CCD5061

Fairchild
Part Number CCD5061
Manufacturer Fairchild
Description 6K x 128 Element / TDI-Time / Delay and Integration Sensor
Published Jun 27, 2005
Detailed Description PRELIMINARY DATA SHEET CCD5061 6K x 128 Element TDI – Time, Delay and Integration Sensor FEATURES • • • • • • • • 6144...
Datasheet PDF File CCD5061 PDF File

CCD5061
CCD5061

Overview
PRELIMINARY DATA SHEET CCD5061 6K x 128 Element TDI – Time, Delay and Integration Sensor FEATURES • • • • • • • • 6144 pixels per line 128 lines of integration 8.
75µm x 8.
75µm pixel size # of TDI stages selectable from 128, 64, 32, 16, 8, 4 Bi-directional TDI line shifting (shift up or down) 4 outputs—each capable of 20MHz data rate—80MHz total data rate 100% fill factor On-chip binning capability GENERAL DESCRIPTION The CCD5061 is a 6144 pixel x 128 line, high speed TDI sensor.
The active imaging area is organized as 6144 vertical columns and 128 horizontal TDI rows.
The array is set up for bi-directional operation.
There are identical output registers and amplifiers on both the top and the bottom of the array.
The outputs to be used (either top or bottom) are user-selectable and controlled by the vertical clock phasing.
In addition, the exposure level can be controlled by reducing the number of TDI rows from 128 to 64, 32, 16, 8 or 4.
This is also userselectable and is accomplished by supplying the appropriate phasing for the vertical clocks within each section.
For instance, if 64 lines of TDI were required, the vertical clocks for lines 65-128 would be connected to a high potential, which would drain these unused rows out to the opposite side (unused) of the array to be dumped in the drain.
With four outputs, each running at 20MHz, the CCD5061 can provide a total data rate of 80MHz enabling the CCD to run at better than 12KHz line rate.
Utilizing Fairchild Imaging proprietary buried channel CCD process, the CCD5061 achieves consistent, superior TDI performance.
The active imaging area is separated from the four horizontal output registers by 21 isolation rows.
These isolation rows are covered by a metal lightshield to protect them while charge transfers to the output registers.
Both the active imaging area and the isolation region utilize 3-phase clocking.
The four horizontal output registers utilize 4phase clocking.
Special design techniques have been implem...


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