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CCD5061

Fairchild Imaging
Part Number CCD5061
Manufacturer Fairchild Imaging
Description 6k x 128 Element Time Delay Integration Sensor
Published Jan 20, 2015
Detailed Description Fairchild Imaging CCD 5061 6k x 128 Element, Time Delay Integration Sensor PRODUCT DESCRIPTION The CCD5061 is a 6144 pi...
Datasheet PDF File CCD5061 PDF File

CCD5061
CCD5061


Overview
Fairchild Imaging CCD 5061 6k x 128 Element, Time Delay Integration Sensor PRODUCT DESCRIPTION The CCD5061 is a 6144 pixel x 128 line, high speed TDI sensor.
The active imaging area is organized as 6144 vertical columns and 128 horizontal TDI rows.
The array is set up for bi-directional operation.
There are identical output registers and amplifiers on both the top and the bottom of the array.
The outputs to be used (either top or bottom) are user-selectable and controlled by the vertical clock timing.
In addition, the exposure level can be controlled by reducing the number of TDI rows from 128 to 96, 64, 32, 16, 8 or 4.
This is also user-selectable and is accomplished by supplying the appropriate phasing for the vertical clocks within each section.
For instance, if 64 lines of TDI were required, the vertical clocks for lines 65-128 would be connected to a high potential, which would drain these unused rows out to the opposite side (unused) of the array to be dumped into the VOFD drain.
With four outputs, each running at 20MHz, the CCD5061 can provide a total data rate of 80MHz enabling the CCD to run at better than 12kHz line rate.
Utilizing Fairchild Imaging proprietary buried channel CCD process, the CCD5061 achieves consistent, superior TDI performance.
The active imaging area is separated from the four horizontal output registers by 21 isolation rows.
These isolation rows are covered by a metal lightshield to protect them while charge transfers to the output registers.
Both the active imaging area and the isolation region utilize 3-phase clocking.
The four horizontal output registers utilize 4-phase clocking.
Special design techniques have been implemented to maximize charge transfer efficiency especially at low light levels.
The output amplifier is a 3-stage source follower configuration.
This allows maximum scale factor (charge to voltage conversion) and maximum bandwidth.
The CCD5061 is housed in a custom 176 pin (100 mil grid) ceramic PGA package.
It has a...


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