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MC74VHC393

Motorola
Part Number MC74VHC393
Manufacturer Motorola
Description Dual 4-Bit Binary Ripple Counter
Published Oct 12, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 4-Bit Binary Ripple Counter The MC74VHC393 is an advanced high speed CMOS d...
Datasheet PDF File MC74VHC393 PDF File

MC74VHC393
MC74VHC393


Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 4-Bit Binary Ripple Counter The MC74VHC393 is an advanced high speed CMOS dual 4–bit binary ripple counter fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
This device consists of two independent 4–bit binary ripple counters with parallel outputs from each counter stage.
A ÷256 counter can be obtained by cascading the two binary counters.
Internal flip–flops are triggered by high–to–low transitions of the clock input.
Reset for the counters is asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the VHC393.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• • • • • • • • • • • High Speed: fmax = 170MHz (Typ) at VCC = 5V Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.
5V Operating Range Low Noise: VOLP = 0.
8V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 236 FETs or 59 Equivalent Gates MC74VHC393 D SUFFIX 14–LEAD SOIC PACKAGE CASE 751A–03 DT SUFFIX 14–LEAD TSSOP PACKAGE CASE 948G–01 M SUFFIX 14–LEAD SOIC EIAJ PACKAGE CASE 965–01 ORDERING INFORMATION MC74VHCXXXD MC74VHCXXXDT MC74VHCXXXM SOIC TSSOP SOIC EIAJ PIN ASSIGNMENT LOGIC DIAGRAM CP1 BINARY COUNTER 3, 11 4, 10 5, 9 6, 8 2, 12 nQA nQB nQC nQD RD1 1QA 1QB 1QC 1QD RDn GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC CP2 RD2 2QA 2QB 2QC 2QD CPn 1, 13 FUNCTION TABLE Inputs Clock X H L ↑ ↓ Reset H L L L L Outputs L No Change No Change No Chang...



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