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MC74VHC373

Motorola
Part Number MC74VHC373
Manufacturer Motorola
Description Octal D-Type Latch
Published Oct 12, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D-Type Latch with 3-State Output The MC74VHC373 is an advanced high speed ...
Datasheet PDF File MC74VHC373 PDF File

MC74VHC373
MC74VHC373

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D-Type Latch with 3-State Output The MC74VHC373 is an advanced high speed CMOS octal latch with 3–state output fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
This 8–bit D–type latch is controlled by a latch enable input and an output enable input.
When the output enable input is high, the eight outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• • • • • • • • • • • High Speed: tPD = 5.
0ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.
5V Operating Range Low Noise: VOLP = 0.
9V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 186 FETs or 46.
5 Equivalent Gates MC74VHC373 DW SUFFIX 20–LEAD SOIC PACKAGE CASE 751D–04 DT SUFFIX 20–LEAD TSSOP PACKAGE CASE 948E–02 M SUFFIX 20–LEAD SOIC EIAJ PACKAGE CASE 967–01 ORDERING INFORMATION MC74VHCXXXDW SOIC MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS PIN ASSIGNMENT OE Q0 D0 D1 Q1 Q2 D2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE LE OE 11 1 D3 Q3 GND FUNCTION TABLE INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L No Change Z 6/97 © Motorola, Inc.
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