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SI5013

Silicon Laboratories
Part Number SI5013
Manufacturer Silicon Laboratories
Description OC-12/3 / STM-4/1 SONET/SDH CDR
Published Nov 11, 2005
Detailed Description Si5013 OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER Features High-speed clock and data recovery device w...
Datasheet PDF File SI5013 PDF File

SI5013
SI5013

Overview
Si5013 OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER Features High-speed clock and data recovery device with integrated limiting amplifier: Supports OC-12/3, STM-4/1 Loss-of-signal level alarm DSPLL® technology Data slicing level control Jitter generation 2.
3 mUIrms (typ) Small footprint: 5 x 5 mm 10 mVPP differential sensitivity 3.
3 V supply Reference and reference-less operation supported Applications SONET/SDH/ATM routers Add/drop multiplexers Digital cross connects Board level serial links SONET/SDH test equipment Optical transceiver modules SONET/SDH regenerators Description The Si5013 is a fully-integrated, high-performance limiting amplifier (LA) and clock and data recovery (CDR) IC for high-speed serial communication systems.
It derives timing information and data from a serial input at OC-12/3 and STM-4/1 rates.
Use of an external reference clock is optional.
Silicon Laboratories DSPLL® technology eliminates sensitive noise entry points, thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance.
The Si5013 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs.
It operates from a 3.
3 V supply over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram LTR LOS DSQLCH VDD DIN+ DIN– VDD Ordering Information: See page 22.
Pin Assignments Si5013 NC BER_ALM BER_LVL VDD CLKDSBL CLKOUT+ CLKOUT– 28 27 26 25 24 23 22 RATESEL 1 21 VDD GND 2 20 REXT LOS_LVL 3 SLICE_LVL 4 REFCLK+ 5 GND Pad 19 RESET/CAL 18 VDD 17 DOUT+ REFCLK– 6 16 DOUT– LOL 7 15 TDI 8 9 10 11 12 13 14 LOS_LVL LOS DIN+ DIN– REFCLK+ REFCLK– (Optional) Signal Detect Retimer 2 BUF 2 Limiting Amp DSPLL BER Monitor 2 BUF 2 Lock Detection Bias Gen.
Reset/ Calibration SLICE_LVL BER_ALM REXT LTR BER_LVL RATESEL LOL RESET/CAL DSQLCH DOUT+ DOUT– CLKOUT+ CLKOUT– CLK_DSBL Rev.
1.
6 6/08 Copyright © 2008 by Silicon Laboratories Si50...


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