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DS1200

Dallas Semiconducotr
Part Number DS1200
Manufacturer Dallas Semiconducotr
Description Serial RAM Chip
Published Dec 6, 2005
Detailed Description DS1200 Serial RAM Chip www.maxim-ic.com FEATURES § § § § § § § § § § § § § 1024 Bits of Read/Write Memory Low Data Rete...
Datasheet PDF File DS1200 PDF File

DS1200
DS1200

Overview
DS1200 Serial RAM Chip www.
maxim-ic.
com FEATURES § § § § § § § § § § § § § 1024 Bits of Read/Write Memory Low Data Retention Current for Battery Backup Applications Four Million Bits/Second Data Rate Single-Byte or Multiple-Byte Data Transfer Capability No Restrictions on the Number of Write Cycles Low-Power CMOS Circuitry PIN ASSIGNMENT 16-Pin SO (300mil) See Mech.
Drawings Section APPLICATIONS Software Authorization Computer Identification System Access Control Secure Personnel Areas Calibration Automatic System Setup Traveling Work Record PIN DESCRIPTION VCC RST DQ CLK GND VBAT NC - +5V - Reset - Data Input/Output - Clock - Ground - Battery (+) - No Connection DESCRIPTION The DS1200 serial RAM chip is a miniature read/write memory that can randomly access individual 8-bit strings (bytes) or sequentially access the entire 1024-bit contents (burst).
Interface cost to a microprocessor is minimized by on-chip circuitry, which permits data transfers with only three signals: CLK, RST , and DQ.
Nonvolatility can be achieved by connecting a battery of 2V to 4V at the battery input VBAT.
A load of 0.
5mA should be used to size the external battery for the required data retention time.
If nonvolatility is not required the VBAT pin should be grounded.
1 of 7 092702 DS1200 Figure 1.
ELECTRONIC TAG BLOCK DIAGRAM Figure 2.
ADDRESS/COMMAND 7 B 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 5 4 3 2 1 0 7 R W 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W A6 A5 A4 A3 A2 A1 A0 B-BURST R-READ W-WRITE BYTE 3 BYTE 2 BYTE 1 OPERATION The block diagram (Figure 1) illustrates the main elements of the device: shift register, control logic, NV RAM, and power switch.
To initiate a memory cycle, RST is taken high and 24 bits are loaded into the shift register, providing both address and command information.
Each bit is input serially on the rising edge of the CLK input.
Seven address bits specify one of the 128 RAM locations.
The remaining command bits specify read/write and byte/burst mode.
A...


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