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IN16C554

IK Semiconductor
Part Number IN16C554
Manufacturer IK Semiconductor
Description TQ Enhanced Quadruple 16C550 UART
Published Jan 15, 2006
Detailed Description 1. General Description IN16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Tra...
Datasheet PDF File IN16C554 PDF File

IN16C554
IN16C554

Overview
1.
General Description IN16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter).
w status of the UART at any time during the functional operation.
The Status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions such as parity, overrun, framing, and break interrupt.
IN16C554 includes a programmable baud rate generator which is capable of dividing the timing reference clock input by divisors of 1 to 216-1, and producing a 16x clock for driving the internal transmitter logic.
Provisions are also included to use this clock to drive the receiver logic.
IN16C554 has complete MODEM-control capability and an interrupt system that can be programmed to the user’s requirements, minimizing the computing required to handle the communication links.
a D .
Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a w MODEM, and parallel-to-serial conversion on data characters received from the CPU.
The CPU can read the complete w FIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes.
Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead.
In this mode, internal S a t e e h U 4 t m o .
c IN16C554PL/IN16C554TQ QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT 2.
Features z z z z z z z z number of interrupts to CPU.
In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
Holding Register and Shift Register eliminate need for precise synchronization between the CPU and serial data.
Independently controlled transmit, receive, line status and data interrupts.
Programmable Baud Rate Generators which allow division of any input reference clock by 1 to 216-1 and gen...


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