DatasheetsPDF.com

IN16C554A

IK Semiconductor
Part Number IN16C554A
Manufacturer IK Semiconductor
Description Quadruple UART
Published Feb 27, 2016
Detailed Description 1. Description IN16C554A Quadruple UART February 2009 REV 1.01 IN16C554A is an enhanced quadruple version of the 16C550...
Datasheet PDF File IN16C554A PDF File

IN16C554A
IN16C554A

Overview
1.
Description IN16C554A Quadruple UART February 2009 REV 1.
01 IN16C554A is an enhanced quadruple version of the 16C550UART (Universal Asynchronous Receiver Transmitter).
IN16C554A is in part an upgrade version of IN16C554, as it is designed for 3.
3V only and has AUTO-CTS, AUTO-RTS functions.
In IN16C554A, Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes.
Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU.
The CPU can read the complete status of the UART at any time during the functional operation.
The Status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions such as parity, overrun, framing, and break interrupt.
IN16C554A includes a programmable baud rate generator which is capable of dividing the timing reference clock input by divisors of 1 to 216-1, and producing a 16x clock for driving the internal transmitter logic.
Provisions are also included to use this clock to drive the receiver logic.
IN16C554A has complete MODEM-control capability and an interrupt system that can be programmed to the user’s requirements, minimizing the computing required to handle the communication links.
Moreover IN16C554A can select hardware flow control.
Hardware flow control significantly reduces software overhead and increases system efficiency.
2.
Features ■ In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the number of interrupts to CPU.
■ Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
■ Holding Register and Shift Register eliminate need for precise synchronization between the...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)