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IS42S16400C

ISSI
Part Number IS42S16400C
Manufacturer ISSI
Description 64M-Bit x 16-Bit 4 4-Bank SDRAM
Published Jan 16, 2006
Detailed Description IS42S16400Com .c U Bits x 4 Banks (64-MBIT) 64 Meg Bits x4 16 AUGUST 2004 t e SYNCHRONOUS DYNAMIC RAM e h S FEATURES OVE...
Datasheet PDF File IS42S16400C PDF File

IS42S16400C
IS42S16400C


Overview
IS42S16400Com .
c U Bits x 4 Banks (64-MBIT) 64 Meg Bits x4 16 AUGUST 2004 t e SYNCHRONOUS DYNAMIC RAM e h S FEATURES OVERVIEW a t ISSI's 64Mb Synchronous DRAM IS42S16400C is • Clock frequency: 166, 133 MHz a organized as 1,048,576 bits x 16-bit x 4-bank for improved D • Fully .
synchronous; all signals referenced to a performance.
The synchronous DRAMs achieve high-speed positive w clock edge data transfer using pipeline architecture.
All inputs and wInternal bank for hiding row access/precharge outputs signals refer to the rising edge of the clock input.
• w• Single 3.
3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Self refresh modes ISSI ® • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Industrial temperature availability (133 MHz) • Package: 400-mil 54-pin TSOP II • Lead-free package is available PIN DESCRIPTIONS A0-A11 BA0, BA1 I/O0 to I/O15 CLK CKE CS RAS CAS m o .
c U 4 t e e h S a t a .
D w w w PIN CONFIGURATIONS 54-Pin TSOP (Type II) VDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 GND I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 VDDQ GNDQ VDDQ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 GNDQ VDD WE I/O8 NC GND LDQM CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 CLK NC A9 A8 A7 A6 A5 A4 CKE A11 VDD GND GNDQ VDDQ GNDQ VDDQ UDQM Address Input WE Bank Select Address LDQM VDD GND VDDQ GNDQ NC Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command UDQM Copyright © 2004 Integrated Silicon Solution, Inc.
All rights reserved.
ISSI reserves the right to make changes to this specification an...


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