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PLL205-54

Part Number	PLL205-54
Manufacturer	PhaseLink
Description	Programmable Clock Generator
Published	Feb 9, 2006
Detailed Description	m Preliminary PLL205-54 o c . Programmable Clock Generator for VIA KT-266 Chipset U 4 t FEATURES PIN CONFIGURATION e e •...
Datasheet	PLL205-54 PDF File

Overview

m Preliminary PLL205-54 o c .
Programmable Clock Generator for VIA KT-266 Chipset U 4 t FEATURES PIN CONFIGURATION e e • Generates all clock frequencies for VIA KT266 h chipset.
S a • Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and 10 PCI.
D .
• w Enhanced PCI Output Drive selectable by I2C.
•w One 48MHz clock and 24_48MHz clock via I2C.
w• Three 14.
318MHz reference clocks.
VDD1 GND 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF0/FS0*^ REF1/FS1*^ XIN XOUT REF_F REF_STOP#^ VDD2 48MHz/FS3*^ AGP_STOP#^ GND CPUT0 CPUC0 • • • • • • • • Program 5-bit CPU VID (Voltage Identification) through I2C.
Power management control to stop CPU, PCI, REF, 24_48MHz, 48MHz and AGP clocks.
Supports 2-wire I2C serial bus interface with readback.
Single byte micro-step linear Frequency Programming via I2C with glitch free smooth switching.
Built-in programmable watchdog timer.
Spread Spectrum ± 0.
25% center, ± 0.
5% center, ± 0.
75% center, and 0 to -0.
5% downspread.
50% duty cycle with low jitter.
Available in 300 mil 48 Pin SSOP.
BLOCK DIAGRAM XIN XOUT XTAL OSC FS (0:4)* PLL1 SST m o .
c U 4 t e e h S a t a .
D w w w PCI0 PCI1 GND 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 24_48Mhz/FS4*v GND PCI_F VDDL1 CPUT_CS PLL205-54 CPUC_CS GND PCI2 PCI3 PCI4 PCI5 CPU_STOP#^ PCI_STOP/WDRESET# PD# VDDL2 GND VDD3 PCI6 GND SDATA SCLK GND AGP2 PCI7 PCI8/FS2*^ PCI9_E/SELPCI9_E# VDD3 SEL24_48#^ VIDENB^ VID0^ VID1^ VID2^ AGP1 AGP0 VDD4 GND VDD5 VID4^ VID3^ Note: ^: Pull up v: Pull down #: Active low * : Bi-directional up latched at power-up POWER GROUP • • • • • • • VDD1 REF(0:1) REF_F CPUT0 CPUC0 VDD1: REF(0:1), REF_F, XIN, XOUT VDD2: 48MHz or 24_48MHz VDD3: PCI(0:8), PCI9_E VDD4: AGP(0:2) VDD5: I2C, VID VDDL1: CPUT0, CPUC0, CPUT_CS, CPUC_CS VDDL2: PLL Core VDDL1 Control Logic CPUT_CS CPUC_CS KEY SPECIFICATIONS • • • • • VDD4 AGP (0:2) VDD3 PD PCI...

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